TSMC expands CoWoS/A13

Why it matters

TSMC used its North America Technology Symposium in Santa Clara on April 22 to roll out A13, its next leading-edge chipmaking process, and push its advanced packaging roadmap deeper into the artificial intelligence market. (pr.tsmc.com) A13 is a follow-on to A14, which TSMC introduced in April 2025. TSMC said A13 cuts chip area by 6% versus A14, keeps A14 design rules fully backward compatible, and is scheduled for production in 2029, one year after A14. (pr.tsmc.com 1) (pr.tsmc.com 2) The packaging update is about how multiple chips are wired together after they are manufactured. TSMC’s CoWoS, short for chip-on-wafer-on-substrate, uses a large interposer — a wiring layer under the chips — to connect logic dies and stacked high-bandwidth memory in one package. (3dfabric.tsmc.com) TSMC’s current CoWoS-S platform can handle an interposer up to 3.3 reticle size, or about 2,700 square millimeters. For larger designs, TSMC directs customers to CoWoS-L and CoWoS-R, two variants built to stretch package size and routing capacity further. (3dfabric.tsmc.com) That packaging roadmap has been moving quickly. At the same symposium in 2025, TSMC said it planned to bring 9.5-reticle CoWoS into volume production in 2027, large enough to integrate 12 high-bandwidth memory stacks or more alongside leading-edge logic. (pr.tsmc.com) The sequence matters because artificial intelligence chips are no longer limited mainly by transistor density on one die. They are increasingly constrained by how much memory can sit next to the compute chip, and how fast those pieces can talk inside a single package. (3dfabric.tsmc.com) (pr.tsmc.com) TSMC has been building that message for three straight symposiums. In 2024 it introduced System-on-Wafer, a wafer-level approach aimed at hyperscaler data centers; in 2025 it added SoW-X, a CoWoS-based version it said would reach volume production in 2027. (pr.tsmc.com 1) (pr.tsmc.com 2) A13 also slots into a longer cadence for TSMC’s nanosheet era. The company introduced A16 in 2024 for planned 2026 production, A14 in 2025 for planned 2028 production, and now A13 for 2029, giving chip designers a clearer map for both transistor scaling and package scaling. (pr.tsmc.com 1) (pr.tsmc.com 2) (pr.tsmc.com 3) For customers building large artificial intelligence accelerators, the practical choice is no longer just which process node to use. It is which combination of node, memory stacks, and CoWoS package size can be lined up in time for a product launch. (pr.tsmc.com) (3dfabric.tsmc.com)

Key numbers

• TSMC unveiled its A13 technology and expanded CoWoS (chip‑on‑wafer‑on‑substrate) packaging at its North America symposium.
• (businesswire.com) TSMC used its North America Technology Symposium in Santa Clara on April 22 to roll out A13, its next leading-edge chipmaking process, and push its advanced packaging roadmap deeper into the artificial intelligence market.
• (pr.tsmc.com) A13 is a follow-on to A14, which TSMC introduced in April 2025.
• TSMC said A13 cuts chip area by 6% versus A14, keeps A14 design rules fully backward compatible, and is scheduled for production in 2029, one year after A14.

What happens next

• TSMC used its North America Technology Symposium in Santa Clara on April 22 to roll out A13, its next leading-edge chipmaking process, and push its advanced packaging roadmap deeper into the artificial intelligence market.
• TSMC said A13 cuts chip area by 6% versus A14, keeps A14 design rules fully backward compatible, and is scheduled for production in 2029, one year after A14.
• They are increasingly constrained by how much memory can sit next to the compute chip, and how fast those pieces can talk inside a single package.

Sources

• businesswire.com
• pr.tsmc.com
• pr.tsmc.com 2
• 3dfabric.tsmc.com
• pr.tsmc.com 1

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