M5Stack Unveils RISC-V PoE Controller

Why it matters

The ESP32-P4 at the core of the controller is a significant step up in processing power, featuring a dual-core RISC-V CPU running up to 400 MHz with AI instruction extensions. This is paired with a low-power 40 MHz single-core RISC-V processor, allowing the high-performance cores to remain dormant to conserve energy during less demanding tasks. Power-over-Ethernet simplifies industrial deployments by delivering both data and up to 6W of power over a single Ethernet cable, eliminating the need for separate power supplies. This is particularly advantageous for devices in locations where power outlets are not readily available, reducing installation complexity and cost. The inclusion of MIPI CSI/DSI interfaces is critical for the target applications, as this standard is widely used in smartphones and tablets for high-bandwidth camera and display connections. The ESP32-P4 can handle video resolutions up to 1080p, making it suitable for high-resolution HMI touchscreens and machine vision systems. Unlike many of its predecessors in the ESP32 family, the ESP32-P4 omits built-in Wi-Fi and Bluetooth, focusing instead on high-performance processing and a rich set of wired peripherals. The chip boasts over 50 programmable GPIOs, USB OTG 2.0 HS, Ethernet, and SDIO Host 3.0 support for high-speed connectivity. The adoption of the open-source RISC-V instruction set architecture (ISA) is a key trend in industrial applications. It allows for greater design flexibility, customization for specific workloads, and freedom from the licensing fees and vendor lock-in associated with proprietary architectures.

Key numbers

• M5Stack has released the Unit PoE-P4, a new Power-over-Ethernet controller built on the dual-core RISC-V ESP32-P4.
• The device is aimed at industrial vision and HMI applications, featuring MIPI CSI/DSI interfaces, 16MB Flash, and 32MB PSRAM.
• The ESP32-P4 at the core of the controller is a significant step up in processing power, featuring a dual-core RISC-V CPU running up to 400 MHz with AI instruction extensions.
• This is paired with a low-power 40 MHz single-core RISC-V processor, allowing the high-performance cores to remain dormant to conserve energy during less demanding tasks.

What happens next

• The inclusion of MIPI CSI/DSI interfaces is critical for the target applications, as this standard is widely used in smartphones and tablets for high-bandwidth camera and display connections.

Sources

• has released
• The ESP32-P4 at the core
• Power-over-Ethernet simplifies
• This is particularly
• The inclusion of MIPI
• Unlike many of its predecessors
• The adoption of the open-source

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