Semivision flags fabric-level AI shift
What happened
- On May 26, Semivision argued AI infrastructure is moving from chip-centric design toward fabric-level architectures built around optics, memory fabrics and packaging. - The thread’s clearest claim was that future winners will cut system dependencies through redesign, rather than compete mainly for scarce HBM supply. - CXL, co-packaged optics and optical networking roadmaps are already public through consortium specs and vendor launches.
Why it matters
Semivision used a May 26 X thread to describe a change in how AI systems are being built: away from treating the accelerator as the whole product, and toward treating the rack, memory tier and network fabric as the design object. The post grouped that shift around co-packaged optics, Compute Express Link, optical switching, advanced packaging and disaggregated memory. It argued that performance and economics will increasingly depend on how those pieces are partitioned and connected, not only on how many GPUs or HBM stacks a buyer can secure. That framing lines up with where industry roadmaps are already moving. The CXL Consortium’s public materials describe memory pooling, sharing and fabric capabilities as core parts of newer CXL generations, while Broadcom and Nvidia are both marketing co-packaged optics for large AI clusters as a way to improve bandwidth density and power efficiency. ### Why does “fabric-level” matter if the GPU is still the expensive part? CXL’s own white papers describe memory pooling as the ability to treat CXL-attached memory as a resource that can be allocated across hosts, reducing the need to overprovision each server individually. The consortium says CXL 3.0 added advanced switching and fabric capabilities, and CXL 3.1 added further fabric improvements and memory-expander changes. (computeexpresslink.org) That matters because AI systems are increasingly constrained by utilization, memory locality and interconnect reach rather than by raw accelerator count alone. Microsoft Research said in September 2025 that memory and network limits were restraining AI system performance and reducing GPU utilization, while Semivision’s thread made the same point in industry shorthand: redesign the system to remove bottlenecks instead of assuming more HBM will solve them. (computeexpresslink.org) ### What are CPO, CXL and OCS doing in the same conversation? Broadcom defines co-packaged optics as integrating optics and silicon on a single packaged substrate to address bandwidth and power limits in next-generation data-center systems. Nvidia has made a similar case for silicon photonics, saying co-packaged photonics shortens electrical paths and cuts power versus traditional pluggables in AI networks. (microsoft.com) The networking side is also being rebuilt for AI scale. The Ultra Ethernet Consortium says it is developing an open Ethernet-based stack for AI and high-performance computing, and Nvidia says its Spectrum-X Ethernet Photonics platform is aimed at large AI clusters and million-GPU-scale systems. Optical circuit switching was one of the elements Semivision highlighted because once clusters stretch across rows and halls, the fabric itself becomes part of the compute architecture. (cmsgolive.broadcom.com) That last point is an inference from the vendor and consortium roadmaps, not a direct quote from them. ### Why is this also a packaging story, not just a networking story? Broadcom’s recent product releases tie CPO to switch ASICs, 200G-per-lane roadmaps and 102.4-terabit switching, while also pairing those announcements with 3.5D XPU packaging and PCIe Gen6 connectivity. Nvidia likewise describes co-packaged photonics as a packaging change as much as a networking change, because optics move closer to the switch silicon. (ultraethernet.org) That shifts engineering work toward boundaries: which memory stays local, which moves into a pooled tier, which links stay electrical, which become optical, and what must be co-designed at package level. Semivision’s warning about reducing dependencies rather than just buying more HBM fits that pattern, because packaging, interconnect and memory topology all become levers for avoiding a single constrained component. (investors.broadcom.com) ### Where does that leave engineering services firms? CXL resource libraries and demos already emphasize memory pooling, tiering and fabric management, while optics vendors are pitching interoperability and deployment readiness for AI clusters. That means early commercial demand is likely to show up in architecture studies, package-and-board tradeoffs, memory disaggregation work and subsystem integration before it appears as simple headcount demand. That is an inference from the public roadmaps and demonstrations now on offer. (computeexpresslink.org) The next concrete milestones are already scheduled in public roadmaps. Nvidia says Spectrum-X Ethernet Photonics will be available in the second half of 2026, and the CXL Consortium is now publishing CXL 4.0 materials that extend bandwidth and fabric features beyond the 3.x generation. (nvidia.com) (computeexpresslink.org)
Key numbers
- On May 26, Semivision argued AI infrastructure is moving from chip-centric design toward fabric-level architectures built around optics, memory fabrics and packaging.
- Semivision used a May 26 X thread to describe a change in how AI systems are being built: away from treating the accelerator as the whole product, and toward treating the rack, memory tier and network fabric as the design object.
- The consortium says CXL 3.0 added advanced switching and fabric capabilities, and CXL 3.1 added further fabric improvements and memory-expander changes.
- Broadcom’s recent product releases tie CPO to switch ASICs, 200G-per-lane roadmaps and 102.4-terabit switching, while also pairing those announcements with 3.5D XPU packaging and PCIe Gen6 connectivity.
What happens next
- Semivision used a May 26 X thread to describe a change in how AI systems are being built: away from treating the accelerator as the whole product, and toward treating the rack, memory tier and network fabric as the design object.
- It argued that performance and economics will increasingly depend on how those pieces are partitioned and connected, not only on how many GPUs or HBM stacks a buyer can secure.
- Broadcom defines co-packaged optics as integrating optics and silicon on a single packaged substrate to address bandwidth and power limits in next-generation data-center systems.
Quick answers
What happened in Semivision flags fabric-level AI shift?
On May 26, Semivision argued AI infrastructure is moving from chip-centric design toward fabric-level architectures built around optics, memory fabrics and packaging. The thread’s clearest claim was that future winners will cut system dependencies through redesign, rather than compete mainly for scarce HBM supply. CXL, co-packaged optics and optical networking roadmaps are already public through consortium specs and vendor launches.
Why does Semivision flags fabric-level AI shift matter?
Semivision used a May 26 X thread to describe a change in how AI systems are being built: away from treating the accelerator as the whole product, and toward treating the rack, memory tier and network fabric as the design object. The post grouped that shift around co-packaged optics, Compute Express Link, optical switching, advanced packaging and disaggregated memory. It argued that performance and economics will increasingly depend on how those pieces are partitioned and connected, not only on how many GPUs or HBM stacks a buyer can secure. That framing lines up with where industry roadmaps are already moving. The CXL Consortium’s public materials describe memory pooling, sharing and fabric capabilities as core parts of newer CXL generations, while Broadcom and Nvidia are both marketing co-packaged optics for large AI clusters as a way to improve bandwidth density and power efficiency. Why does “fabric-level” matter if the GPU is still the expensive part? CXL’s own white papers describe memory pooling as the ability to treat CXL-attached memory as a resource that can be allocated across hosts, reducing the need to overprovision each server individually. The consortium says CXL 3.0 added advanced switching and fabric capabilities, and CXL 3.1 added further fabric improvements and memory-expander changes. (computeexpresslink.org) That matters because AI systems are increasingly constrained by utilization, memory locality and interconnect reach rather than by raw accelerator count alone. Microsoft Research said in September 2025 that memory and network limits were restraining AI system performance and reducing GPU utilization, while Semivision’s thread made the same point in industry shorthand: redesign the system to remove bottlenecks instead of assuming more HBM will solve them. (computeexpresslink.org) What are CPO, CXL and OCS doing in the same conversation? Broadcom defines co-packaged optics as integrating optics and silicon on a single packaged substrate to address bandwidth and power limits in next-generation data-center systems. Nvidia has made a similar case for silicon photonics, saying co-packaged photonics shortens electrical paths and cuts power versus traditional pluggables in AI networks. (microsoft.com) The networking side is also being rebuilt for AI scale. The Ultra Ethernet Consortium says it is developing an open Ethernet-based stack for AI and high-performance computing, and Nvidia says its Spectrum-X Ethernet Photonics platform is aimed at large AI clusters and million-GPU-scale systems. Optical circuit switching was one of the elements Semivision highlighted because once clusters stretch across rows and halls, the fabric itself becomes part of the compute architecture. (cmsgolive.broadcom.com) That last point is an inference from the vendor and consortium roadmaps, not a direct quote from them. Why is this also a packaging story, not just a networking story? Broadcom’s recent product releases tie CPO to switch ASICs, 200G-per-lane roadmaps and 102.4-terabit switching, while also pairing those announcements with 3.5D XPU packaging and PCIe Gen6 connectivity. Nvidia likewise describes co-packaged photonics as a packaging change as much as a networking change, because optics move closer to the switch silicon. (ultraethernet.org) That shifts engineering work toward boundaries: which memory stays local, which moves into a pooled tier, which links stay electrical, which become optical, and what must be co-designed at package level. Semivision’s warning about reducing dependencies rather than just buying more HBM fits that pattern, because packaging, interconnect and memory topology all become levers for avoiding a single constrained component. (investors.broadcom.com) Where does that leave engineering services firms? CXL resource libraries and demos already emphasize memory pooling, tiering and fabric management, while optics vendors are pitching interoperability and deployment readiness for AI clusters. That means early commercial demand is likely to show up in architecture studies, package-and-board tradeoffs, memory disaggregation work and subsystem integration before it appears as simple headcount demand. That is an inference from the public roadmaps and demonstrations now on offer. (computeexpresslink.org) The next concrete milestones are already scheduled in public roadmaps. Nvidia says Spectrum-X Ethernet Photonics will be available in the second half of 2026, and the CXL Consortium is now publishing CXL 4.0 materials that extend bandwidth and fabric features beyond the 3.x generation. (nvidia.com) (computeexpresslink.org)
