TSMC packaging pressure
What happened
- TSMC debuted A13 packaging technology and reported heavy bookings for CoWoS advanced packaging capacity. - The company warned of packaging capacity pressure driven by AI chip demand. - Advanced‑packaging bottlenecks could lengthen lead times and constrain supply for multiple AI silicon vendors. (businesswire.com)
Why it matters
The squeeze in artificial intelligence chips has shifted from making silicon to wrapping it together: Taiwan Semiconductor Manufacturing Co. said bookings for its CoWoS packaging are heavy and capacity is under pressure. (businesswire.com) CoWoS, short for chip-on-wafer-on-substrate, is the stage that links a compute die to stacks of high-bandwidth memory inside one package. TSMC says the technology is built for artificial intelligence and supercomputing chips that need dense connections and large interposers to move data fast. (tsmc.com) At its North America Technology Symposium in Santa Clara on April 22, TSMC also introduced its A13 logic process, a direct shrink of A14 with 6% area savings and production planned for 2029. The company said A13 is aimed at next-generation artificial intelligence, high-performance computing, and mobile chips. (businesswire.com) The packaging update matters sooner than A13 does. TSMC said last year that its larger 9.5-reticle CoWoS would enter volume production in 2027 and support packages with 12 high-bandwidth-memory stacks or more, underscoring how fast package size and memory counts are rising. (businesswire.com) TSMC has been signaling this bottleneck for more than a year. In its April 2025 earnings call, the company said it was working to double CoWoS capacity in 2025 to meet customer demand for artificial-intelligence graphics processors, application-specific integrated circuits, and memory controllers. (investor.tsmc.com) That leaves chip designers competing for two scarce things at once: leading-edge wafers and the advanced packaging lines needed after the wafers are finished. Supply-chain reporting from DigiTimes this month said CoWoS capacity remains in severe shortage as artificial-intelligence demand keeps climbing. (digitimes.com) The pressure reaches beyond Nvidia. CoWoS is the packaging base for a widening list of accelerators from cloud companies and custom-chip vendors, and TSMC has positioned it as part of its 3DFabric platform for high-performance computing systems. (tsmc.com) TSMC’s own roadmap shows why the queue is getting longer. In 2024 it introduced System-on-Wafer, in 2025 it said SoW-X would reach volume production in 2027, and in 2026 it paired the A13 debut with another warning that packaging demand is still outrunning supply. (tsmc.com) (businesswire.com 1) (businesswire.com 2) For customers planning 2026 and 2027 launches, the practical question is no longer just who can design the best artificial-intelligence chip. It is who can secure a slot to package it. (businesswire.com)
Key numbers
- TSMC debuted A13 packaging technology and reported heavy bookings for CoWoS advanced packaging capacity.
- (tsmc.com) At its North America Technology Symposium in Santa Clara on April 22, TSMC also introduced its A13 logic process, a direct shrink of A14 with 6% area savings and production planned for 2029.
- The company said A13 is aimed at next-generation artificial intelligence, high-performance computing, and mobile chips.
- (businesswire.com) The packaging update matters sooner than A13 does.
What happens next
- The company said A13 is aimed at next-generation artificial intelligence, high-performance computing, and mobile chips.
- (tsmc.com) (businesswire.com 1) (businesswire.com 2) For customers planning 2026 and 2027 launches, the practical question is no longer just who can design the best artificial-intelligence chip.
- Advanced‑packaging bottlenecks could lengthen lead times and constrain supply for multiple AI silicon vendors.
Quick answers
What happened in TSMC packaging pressure?
TSMC debuted A13 packaging technology and reported heavy bookings for CoWoS advanced packaging capacity. The company warned of packaging capacity pressure driven by AI chip demand. Advanced‑packaging bottlenecks could lengthen lead times and constrain supply for multiple AI silicon vendors. (businesswire.com)
Why does TSMC packaging pressure matter?
The squeeze in artificial intelligence chips has shifted from making silicon to wrapping it together: Taiwan Semiconductor Manufacturing Co. said bookings for its CoWoS packaging are heavy and capacity is under pressure. (businesswire.com) CoWoS, short for chip-on-wafer-on-substrate, is the stage that links a compute die to stacks of high-bandwidth memory inside one package. TSMC says the technology is built for artificial intelligence and supercomputing chips that need dense connections and large interposers to move data fast. (tsmc.com) At its North America Technology Symposium in Santa Clara on April 22, TSMC also introduced its A13 logic process, a direct shrink of A14 with 6% area savings and production planned for 2029. The company said A13 is aimed at next-generation artificial intelligence, high-performance computing, and mobile chips. (businesswire.com) The packaging update matters sooner than A13 does. TSMC said last year that its larger 9.5-reticle CoWoS would enter volume production in 2027 and support packages with 12 high-bandwidth-memory stacks or more, underscoring how fast package size and memory counts are rising. (businesswire.com) TSMC has been signaling this bottleneck for more than a year. In its April 2025 earnings call, the company said it was working to double CoWoS capacity in 2025 to meet customer demand for artificial-intelligence graphics processors, application-specific integrated circuits, and memory controllers. (investor.tsmc.com) That leaves chip designers competing for two scarce things at once: leading-edge wafers and the advanced packaging lines needed after the wafers are finished. Supply-chain reporting from DigiTimes this month said CoWoS capacity remains in severe shortage as artificial-intelligence demand keeps climbing. (digitimes.com) The pressure reaches beyond Nvidia. CoWoS is the packaging base for a widening list of accelerators from cloud companies and custom-chip vendors, and TSMC has positioned it as part of its 3DFabric platform for high-performance computing systems. (tsmc.com) TSMC’s own roadmap shows why the queue is getting longer. In 2024 it introduced System-on-Wafer, in 2025 it said SoW-X would reach volume production in 2027, and in 2026 it paired the A13 debut with another warning that packaging demand is still outrunning supply. (tsmc.com) (businesswire.com 1) (businesswire.com 2) For customers planning 2026 and 2027 launches, the practical question is no longer just who can design the best artificial-intelligence chip. It is who can secure a slot to package it. (businesswire.com)
