Synopsys deepens TSMC tie
What happened
- Synopsys announced broader collaboration with TSMC to deliver silicon‑proven IP and certified EDA flows for advanced nodes. - Synopsys also showed tools integrating Ansys tech to address voltage‑drop and thermal management earlier in design flows. - The move packages process, IP, and multiphysics validation together, creating an attach point for implementation partners who operationalise certified flows (prnewswire.com) (investing.com).
Why it matters
Synopsys said on April 22 it is expanding its work with Taiwan Semiconductor Manufacturing Co. so chip designers can use prequalified building blocks and approved design software on TSMC’s newest processes. (synopsys.com) In chip design, “IP” means reusable parts such as memory interfaces and controller blocks, while “EDA” software is the toolchain engineers use to draw, check, and route a chip before it is manufactured. TSMC’s EDA Alliance says those reference flows are validated with partner tools against its process roadmap. (tsmc.com) Synopsys said the latest expansion covers TSMC’s 3-nanometer and 2-nanometer families, plus A16 with Super Power Rail and A14. The company described the package as silicon-proven IP, artificial-intelligence-enabled design flows, and system-level support for advanced packaging nodes. (synopsys.com) The immediate problem is heat and power. As AI chips pack in more transistors and stack more dies, designers have to catch voltage drop, overheating, and timing errors earlier, before a tape-out locks in expensive mistakes. (ansys.com) Synopsys said its newer flows now pull in Ansys technology to model those effects sooner, including RedHawk-SC, RedHawk-SC Electrothermal, Totem, and HFSS-IC Pro. Those tools are used for power integrity, heat analysis, and electromagnetic checks that become harder as chips move to denser nodes and 3D packaging. (ansys.com) This builds on a year of tighter coordination. In April 2025, Synopsys and TSMC said digital and analog flows were certified on A16 and N2P, with initial work starting on A14; in September 2025, they added certified flows on N2P and A16 using TSMC NanoFlex architecture. (synopsys.com 1) (synopsys.com 2) The packaging piece matters because many AI processors no longer fit on one slab of silicon. Synopsys said its 3DIC Compiler supports TSMC’s CoWoS packaging and 5.5x-reticle interposer sizes, which are used to connect multiple chiplets and high-bandwidth memory in one package. (prnewswire.com) For customers, the pitch is less about a single new tool than a preassembled path: process rules from TSMC, interface blocks from Synopsys, and multiphysics checks from Ansys tied into one flow. That can also create work for implementation partners that take certified flows and turn them into finished chip programs for cloud, networking, and automotive clients. (synopsys.com) (tsmc.com) The deeper tie-up shows where the chip business is heading in 2026: fewer standalone design tools, more bundled stacks that try to reduce risk before the first wafer is ever processed. (synopsys.com)
Key numbers
- Synopsys said on April 22 it is expanding its work with Taiwan Semiconductor Manufacturing Co.
- (tsmc.com) Synopsys said the latest expansion covers TSMC’s 3-nanometer and 2-nanometer families, plus A16 with Super Power Rail and A14.
- Those tools are used for power integrity, heat analysis, and electromagnetic checks that become harder as chips move to denser nodes and 3D packaging.
- In April 2025, Synopsys and TSMC said digital and analog flows were certified on A16 and N2P, with initial work starting on A14; in September 2025, they added certified flows on N2P and A16 using TSMC NanoFlex architecture.
Quick answers
What happened in Synopsys deepens TSMC tie?
Synopsys announced broader collaboration with TSMC to deliver silicon‑proven IP and certified EDA flows for advanced nodes. Synopsys also showed tools integrating Ansys tech to address voltage‑drop and thermal management earlier in design flows. The move packages process, IP, and multiphysics validation together, creating an attach point for implementation partners who operationalise certified flows (prnewswire.com) (investing.com).
Why does Synopsys deepens TSMC tie matter?
Synopsys said on April 22 it is expanding its work with Taiwan Semiconductor Manufacturing Co. so chip designers can use prequalified building blocks and approved design software on TSMC’s newest processes. (synopsys.com) In chip design, “IP” means reusable parts such as memory interfaces and controller blocks, while “EDA” software is the toolchain engineers use to draw, check, and route a chip before it is manufactured. TSMC’s EDA Alliance says those reference flows are validated with partner tools against its process roadmap. (tsmc.com) Synopsys said the latest expansion covers TSMC’s 3-nanometer and 2-nanometer families, plus A16 with Super Power Rail and A14. The company described the package as silicon-proven IP, artificial-intelligence-enabled design flows, and system-level support for advanced packaging nodes. (synopsys.com) The immediate problem is heat and power. As AI chips pack in more transistors and stack more dies, designers have to catch voltage drop, overheating, and timing errors earlier, before a tape-out locks in expensive mistakes. (ansys.com) Synopsys said its newer flows now pull in Ansys technology to model those effects sooner, including RedHawk-SC, RedHawk-SC Electrothermal, Totem, and HFSS-IC Pro. Those tools are used for power integrity, heat analysis, and electromagnetic checks that become harder as chips move to denser nodes and 3D packaging. (ansys.com) This builds on a year of tighter coordination. In April 2025, Synopsys and TSMC said digital and analog flows were certified on A16 and N2P, with initial work starting on A14; in September 2025, they added certified flows on N2P and A16 using TSMC NanoFlex architecture. (synopsys.com 1) (synopsys.com 2) The packaging piece matters because many AI processors no longer fit on one slab of silicon. Synopsys said its 3DIC Compiler supports TSMC’s CoWoS packaging and 5.5x-reticle interposer sizes, which are used to connect multiple chiplets and high-bandwidth memory in one package. (prnewswire.com) For customers, the pitch is less about a single new tool than a preassembled path: process rules from TSMC, interface blocks from Synopsys, and multiphysics checks from Ansys tied into one flow. That can also create work for implementation partners that take certified flows and turn them into finished chip programs for cloud, networking, and automotive clients. (synopsys.com) (tsmc.com) The deeper tie-up shows where the chip business is heading in 2026: fewer standalone design tools, more bundled stacks that try to reduce risk before the first wafer is ever processed. (synopsys.com)
