Samsung Foundry + Cadence chiplet tie
What happened
- Samsung Foundry announced a partnership with Cadence focused on chiplet‑based platforms for next‑gen computing and AI. - The collaboration emphasizes design flows that simplify chiplet integration for complex AI SoCs. - Partnering on chiplet tooling shortens integration timelines for customers moving to multi‑die AI packages. (x.com)
Why it matters
Chiplets split a big processor into smaller dies, then wire them together inside one package like Lego blocks for computing. Samsung Foundry and Cadence are now building more of that stack together for artificial intelligence chips. (cadence.com) Cadence said on January 6, 2026 that Samsung Foundry is one of the strategic partners in its new “Chiplet Spec-to-Packaged Parts” ecosystem, aimed at reducing engineering complexity and speeding time to market for chiplets used in physical artificial intelligence, data centers, and high-performance computing. (cadence.com) Samsung said this month that it is co-developing a silicon prototype of Cadence’s physical artificial intelligence chiplet platform on Samsung’s SF5A process, with pre-verified partner intellectual property already integrated into the design. (samsung.com) A system on a chip packs computing, memory links, and input-output blocks onto one piece of silicon; chiplets break that job into smaller pieces so companies can mix and match functions and avoid building one giant die. Cadence said that approach can improve reuse, power tuning, and manufacturing yield in edge, industrial, automotive, and data-center designs. (samsung.com) The companies are pitching that model at a moment when artificial intelligence chips are getting larger, hotter, and harder to route across a single die. Cadence said its broader Samsung collaboration already covers system-on-chip, three-dimensional integrated circuit, and chiplet design flows on Samsung’s SF2P and other advanced nodes. (cadence.com) That earlier expansion, announced June 16, 2025, also included a new multi-year agreement to broaden Cadence memory and interface intellectual property on Samsung Foundry’s SF4X, SF5A, and SF2P processes. (cadence.com) Cadence’s newer chiplet push adds other partners too, including Arm, and centers on pre-validated pieces that can move from architecture planning to packaged silicon with fewer custom integration steps. Cadence said the target markets include physical artificial intelligence, data centers, and high-performance computing. (cadence.com) Samsung’s contribution is the manufacturing side: foundry process technology, packaging know-how, and a prototype vehicle on SF5A that Cadence and its partners can use to show customers a working multi-die path instead of a slide deck. Samsung said the prototype is meant to demonstrate SF5A’s fit for physical artificial intelligence designs. (samsung.com) The immediate test is whether customers adopt those pre-integrated building blocks for real products, not just demonstrations. For Samsung, the bet is that easier chiplet assembly helps pull more artificial intelligence and high-performance computing designs onto its foundry roadmap. (cadence.com)
Key numbers
- (cadence.com) Samsung said this month that it is co-developing a silicon prototype of Cadence’s physical artificial intelligence chiplet platform on Samsung’s SF5A process, with pre-verified partner intellectual property already integrated into the design.
- Cadence said its broader Samsung collaboration already covers system-on-chip, three-dimensional integrated circuit, and chiplet design flows on Samsung’s SF2P and other advanced nodes.
- (cadence.com) That earlier expansion, announced June 16, 2025, also included a new multi-year agreement to broaden Cadence memory and interface intellectual property on Samsung Foundry’s SF4X, SF5A, and SF2P processes.
- (cadence.com) Samsung’s contribution is the manufacturing side: foundry process technology, packaging know-how, and a prototype vehicle on SF5A that Cadence and its partners can use to show customers a working multi-die path instead of a slide deck.
What happens next
- Cadence said the target markets include physical artificial intelligence, data centers, and high-performance computing.
- (cadence.com) - Samsung Foundry announced a partnership with Cadence focused on chiplet‑based platforms for next‑gen computing and AI.
Quick answers
What happened in Samsung Foundry + Cadence chiplet tie?
Samsung Foundry announced a partnership with Cadence focused on chiplet‑based platforms for next‑gen computing and AI. The collaboration emphasizes design flows that simplify chiplet integration for complex AI SoCs. Partnering on chiplet tooling shortens integration timelines for customers moving to multi‑die AI packages. (x.com)
Why does Samsung Foundry + Cadence chiplet tie matter?
Chiplets split a big processor into smaller dies, then wire them together inside one package like Lego blocks for computing. Samsung Foundry and Cadence are now building more of that stack together for artificial intelligence chips. (cadence.com) Cadence said on January 6, 2026 that Samsung Foundry is one of the strategic partners in its new “Chiplet Spec-to-Packaged Parts” ecosystem, aimed at reducing engineering complexity and speeding time to market for chiplets used in physical artificial intelligence, data centers, and high-performance computing. (cadence.com) Samsung said this month that it is co-developing a silicon prototype of Cadence’s physical artificial intelligence chiplet platform on Samsung’s SF5A process, with pre-verified partner intellectual property already integrated into the design. (samsung.com) A system on a chip packs computing, memory links, and input-output blocks onto one piece of silicon; chiplets break that job into smaller pieces so companies can mix and match functions and avoid building one giant die. Cadence said that approach can improve reuse, power tuning, and manufacturing yield in edge, industrial, automotive, and data-center designs. (samsung.com) The companies are pitching that model at a moment when artificial intelligence chips are getting larger, hotter, and harder to route across a single die. Cadence said its broader Samsung collaboration already covers system-on-chip, three-dimensional integrated circuit, and chiplet design flows on Samsung’s SF2P and other advanced nodes. (cadence.com) That earlier expansion, announced June 16, 2025, also included a new multi-year agreement to broaden Cadence memory and interface intellectual property on Samsung Foundry’s SF4X, SF5A, and SF2P processes. (cadence.com) Cadence’s newer chiplet push adds other partners too, including Arm, and centers on pre-validated pieces that can move from architecture planning to packaged silicon with fewer custom integration steps. Cadence said the target markets include physical artificial intelligence, data centers, and high-performance computing. (cadence.com) Samsung’s contribution is the manufacturing side: foundry process technology, packaging know-how, and a prototype vehicle on SF5A that Cadence and its partners can use to show customers a working multi-die path instead of a slide deck. Samsung said the prototype is meant to demonstrate SF5A’s fit for physical artificial intelligence designs. (samsung.com) The immediate test is whether customers adopt those pre-integrated building blocks for real products, not just demonstrations. For Samsung, the bet is that easier chiplet assembly helps pull more artificial intelligence and high-performance computing designs onto its foundry roadmap. (cadence.com)
