TSMC onshores advanced packaging
What happened
- TSMC plans to open a chip‑packaging plant in Arizona by 2029 to handle advanced integration work. - The facility targets advanced packaging, the integration layer that combines compute dies and memory. - The company is also delaying high‑NA EUV adoption over cost concerns, highlighting packaging as the near‑term bottleneck for AI accelerators (reuters.com) (bloomberg.com)
Why it matters
Taiwan Semiconductor Manufacturing Co. plans to add advanced chip packaging in Arizona by 2029, bringing another critical step of artificial-intelligence chipmaking to the U.S. (reuters.com) Deputy co-chief operating officer Kevin Zhang said on April 22 that TSMC aims to build the packaging plant next to its Phoenix fabs. Reuters reported the site would handle “advanced packaging,” the stage that links separate chip pieces into one working processor. (reuters.com) Chip packaging used to mean sealing a finished chip in a protective case. In artificial-intelligence systems, it now also means stacking and wiring compute dies and high-bandwidth memory so they can act like one larger engine. (reuters.com) That step has become a constraint for Nvidia and other AI chip designers because the fastest accelerators need both leading-edge silicon and scarce packaging capacity. TSMC’s CoWoS packaging line has been one of the tightest choke points in the AI supply chain since demand surged in 2023 and 2024. (reuters.com) The Arizona move extends a U.S. expansion that already includes three fabrication plants. TSMC says its first Arizona fab is set to start 4-nanometer production in the first half of 2025, its second fab is planned for 2-nanometer and 3-nanometer production in 2028, and a third fab broke ground in April 2025 for N2 and A16 technologies by the end of the decade. (tsmc.com) TSMC said on March 4, 2025 that it would expand its total U.S. investment to $165 billion, up from the previously announced $65 billion in Arizona. The company said that plan covered three new fabs, two advanced packaging facilities and a major research-and-development center. (tsmc.com) The packaging decision landed as TSMC also signaled less urgency around another expensive tool: ASML’s newest lithography machines. Bloomberg reported Zhang said TSMC has no current plan to use high-numerical-aperture extreme ultraviolet tools through 2029 because the machines are too costly. (bloomberg.com) Bloomberg said those high-NA EUV systems cost more than €350 million, or about $410 million, each. TSMC instead said its A14 process in 2028 and A13 process in 2029 can move ahead without that latest generation of lithography gear. (bloomberg.com) That leaves packaging, not just transistor scaling, at the center of the next AI buildout. By 2029, the question in Arizona is no longer only whether TSMC can print advanced chips in the U.S., but whether it can finish assembling the most valuable ones there too. (reuters.com) (tsmc.com)
Key numbers
- TSMC plans to open a chip‑packaging plant in Arizona by 2029 to handle advanced integration work.
- plans to add advanced chip packaging in Arizona by 2029, bringing another critical step of artificial-intelligence chipmaking to the U.S.
- (reuters.com) Deputy co-chief operating officer Kevin Zhang said on April 22 that TSMC aims to build the packaging plant next to its Phoenix fabs.
- TSMC’s CoWoS packaging line has been one of the tightest choke points in the AI supply chain since demand surged in 2023 and 2024.
What happens next
- plans to add advanced chip packaging in Arizona by 2029, bringing another critical step of artificial-intelligence chipmaking to the U.S.
- (reuters.com) Deputy co-chief operating officer Kevin Zhang said on April 22 that TSMC aims to build the packaging plant next to its Phoenix fabs.
- (tsmc.com) TSMC said on March 4, 2025 that it would expand its total U.S.
Quick answers
What happened in TSMC onshores advanced packaging?
TSMC plans to open a chip‑packaging plant in Arizona by 2029 to handle advanced integration work. The facility targets advanced packaging, the integration layer that combines compute dies and memory. The company is also delaying high‑NA EUV adoption over cost concerns, highlighting packaging as the near‑term bottleneck for AI accelerators (reuters.com) (bloomberg.com)
Why does TSMC onshores advanced packaging matter?
Taiwan Semiconductor Manufacturing Co. plans to add advanced chip packaging in Arizona by 2029, bringing another critical step of artificial-intelligence chipmaking to the U.S. (reuters.com) Deputy co-chief operating officer Kevin Zhang said on April 22 that TSMC aims to build the packaging plant next to its Phoenix fabs. Reuters reported the site would handle “advanced packaging,” the stage that links separate chip pieces into one working processor. (reuters.com) Chip packaging used to mean sealing a finished chip in a protective case. In artificial-intelligence systems, it now also means stacking and wiring compute dies and high-bandwidth memory so they can act like one larger engine. (reuters.com) That step has become a constraint for Nvidia and other AI chip designers because the fastest accelerators need both leading-edge silicon and scarce packaging capacity. TSMC’s CoWoS packaging line has been one of the tightest choke points in the AI supply chain since demand surged in 2023 and 2024. (reuters.com) The Arizona move extends a U.S. expansion that already includes three fabrication plants. TSMC says its first Arizona fab is set to start 4-nanometer production in the first half of 2025, its second fab is planned for 2-nanometer and 3-nanometer production in 2028, and a third fab broke ground in April 2025 for N2 and A16 technologies by the end of the decade. (tsmc.com) TSMC said on March 4, 2025 that it would expand its total U.S. investment to $165 billion, up from the previously announced $65 billion in Arizona. The company said that plan covered three new fabs, two advanced packaging facilities and a major research-and-development center. (tsmc.com) The packaging decision landed as TSMC also signaled less urgency around another expensive tool: ASML’s newest lithography machines. Bloomberg reported Zhang said TSMC has no current plan to use high-numerical-aperture extreme ultraviolet tools through 2029 because the machines are too costly. (bloomberg.com) Bloomberg said those high-NA EUV systems cost more than €350 million, or about $410 million, each. TSMC instead said its A14 process in 2028 and A13 process in 2029 can move ahead without that latest generation of lithography gear. (bloomberg.com) That leaves packaging, not just transistor scaling, at the center of the next AI buildout. By 2029, the question in Arizona is no longer only whether TSMC can print advanced chips in the U.S., but whether it can finish assembling the most valuable ones there too. (reuters.com) (tsmc.com)
