TSMC A13, packaging push
- TSMC unveiled its A13 process and said CoWoS packaging will scale to 5.5‑reticle‑size and larger packages. - The firm also said it can shrink chips without adopting ASML's expensive high‑NA EUV tools for now. - Investors cheered, sending TSMC shares up roughly 5%, while the decision signals delayed high‑NA investment. ( )
A chip factory prints patterns onto silicon the way a projector throws an image onto a screen, and Taiwan Semiconductor Manufacturing Co. said on April 22 it can keep shrinking those patterns without buying ASML’s newest projector yet. (tsmc.com, bloomberg.com) At its North America Technology Symposium in Santa Clara, California, TSMC introduced A13, a process scheduled for production in 2029 that it said is a direct shrink of A14, the node it announced in 2025. TSMC said A13 offers 6% area savings from A14, with design rules that stay backward compatible so customers can move existing designs more quickly. (tsmc.com) The company also put fresh numbers on advanced packaging, the step that bundles compute chips and memory together after the chips are made. TSMC said it is already producing 5.5-reticle-size Chip on Wafer on Substrate, or CoWoS, packages and plans 14-reticle-size CoWoS in 2028, large enough for about 10 compute dies and 20 high-bandwidth memory stacks. (tsmc.com, focustaiwan.tw) That packaging roadmap tracks the current artificial-intelligence race, where performance depends not only on smaller transistors but on how much memory can sit beside the processor in one module. TSMC said larger CoWoS and wafer-scale SoW-X packages are targeted for 2029, alongside more advanced System on Integrated Chips, or SoIC, 3D stacking. (tsmc.com, focustaiwan.tw) The other message was about tools. TSMC Deputy Co-Chief Operating Officer Kevin Zhang told reporters the company has no current plan to use ASML’s high-numerical-aperture extreme ultraviolet machines through 2029 because it can still “harvest the benefit” from current EUV systems and the new tools are “very, very expensive.” (bloomberg.com, theedgesingapore.com) Bloomberg reported those high-NA EUV machines cost more than €350 million, or about $410 million, each. Reuters reported TSMC said it expects to keep making smaller, faster chips with its existing generation of EUV equipment instead. (bloomberg.com, reuters.com) Investors rewarded the update in New York trading on April 22. TSMC’s U.S.-listed shares closed at $387.44, up 5.26% for the day, while ASML’s U.S.-listed shares fell to $1,443.66 after the report on delayed high-NA adoption. (finance.yahoo.com, google.com, wsj.com) ASML still expects high-NA tools to enter high-volume production in 2027 and 2028, according to reporting on the TSMC comments, so TSMC’s stance does not end that rollout. It does show that the industry’s biggest foundry is trying to get another generation of gains from cheaper equipment while it spends heavily on packaging capacity for artificial-intelligence chips. (theedgesingapore.com, tsmc.com)
