TSMC packaging push

Taiwan Semiconductor Manufacturing Co. plans to add an advanced chip-packaging plant in Arizona by 2029, extending its U.S. buildout beyond wafer fabrication. (usnews.com) The new Arizona site is meant to handle advanced packaging, the step that binds several pieces of silicon and memory into one processor package for artificial intelligence chips. Reuters reported the facility is expected to use CoWoS and 3D chip-stacking methods that TSMC already uses for customers including Nvidia. (finance.yahoo.com) (tsmc.com) Packaging has become a choke point because many AI processors are no longer one chip; they are multiple compute dies and high-bandwidth memory stacks assembled into one module. TSMC said in January it was applying for permits for its first advanced-packaging plant in an existing Arizona facility, and Reuters reported on April 22 that the target opening is now 2029. (economictimes.indiatimes.com) (usnews.com) At the same Santa Clara event, TSMC said it will wait until at least 2029 to use ASML’s newest High-NA extreme ultraviolet lithography tools, which are used to print smaller chip features. Kevin Zhang, TSMC’s deputy co-chief operating officer, said the machines are too expensive for the company’s current roadmap. (usnews.com) (bloomberg.com) Bloomberg reported those High-NA systems sell for more than €350 million, or about $410 million, each. TSMC instead said it can keep improving chip density and power efficiency through 2029 with its current extreme ultraviolet tools and process tweaks. (bloomberg.com) (businesswire.com) TSMC used the same event to unveil its A13 process, which it said is scheduled for production in 2029. The company said A13 will deliver up to 20% lower power at the same speed, or up to 15% higher speed at the same power, plus logic density gains over N2. (businesswire.com) Arizona is already central to TSMC’s U.S. expansion. The company said in March 2025 it would raise its total U.S. investment to $165 billion, adding three more fabs, two advanced-packaging facilities, and a research center to its Phoenix plans. (pr.tsmc.com) TSMC’s first Arizona fab has started volume production on 4-nanometer chips, and its second fab was completed in April 2026 with volume production planned for the second half of 2027. The packaging plant would keep more of the AI chip supply chain in the United States instead of sending finished wafers back to Taiwan for assembly. (pr.tsmc.com) (usatoday.com) (finance.yahoo.com) The split decision — more money for packaging in Arizona, no High-NA purchase before 2029 — puts TSMC’s priorities on the slower parts of the production chain. For AI customers, that means the limiting factor is still often where chips get assembled and how much that assembly costs, not just how small the transistors are. (finance.yahoo.com) (usnews.com)