SiFive unveils P570 Gen3 RISC-V core

SiFive on May 12 unveiled its Performance P570 Gen 3, a new out-of-order RISC-V CPU core aimed at edge AI, high-end consumer devices and commercial IoT systems. The Santa Clara, California-based company said the core is fully compliant with the RVA23 profile, a ratified RISC-V application-processor baseline designed for systems that run rich operating systems such as Linux. (sifive.com) SiFive said the design combines a 3-wide, 13-stage superscalar pipeline with a 128-bit vector engine and support for system features including the RISC-V Advanced Interrupt Architecture, WorldGuard and a second-generation RISC-V IOMMU. Krste Asanovic, SiFive’s co-founder and chief architect, said the core was built for “demanding consumer and commercial applications.” (sifive.com) ### Why is SiFive stressing “RVA23-compliant” in this launch? RISC-V International ratified the RVA23 profile in October 2024 as a common software target for 64-bit application processors that run standard binary operating-system distributions. The profile is meant to reduce fragmentation by defining a large guaranteed set of ISA features and a smaller set of discoverable options, according to the RISC-V specifications library. SiFive said the P570 Gen 3 supports all RVA23 mandatory requirements, including the Hypervisor and Vector extensions, and called out backing for the profile from Google, Red Hat and Canonical. The company said that baseline should make the core easier to target for mainstream application development. (sifive.com) ### What does the core itself add over earlier SiFive designs? SiFive said the P570 Gen 3 delivers a 7% to 13% improvement on SpecInt 2006-2017 combined workloads while cutting dynamic power by 13% versus the first-generation P550. The company also said the 128-bit vector pipeline doubles Geekbench performance and can deliver up to 21 times more performance in specific AI-relevant workloads versus Gen 1, and up to 4.5 times versus Gen 2, using dot-product instructions for convolution and matrix multiplication. (riscv.org) A May 12 SiFive engineering blog said the third generation also adds a three-level memory hierarchy. The company said the design can include a shared level-2 cache across up to four cores in a cluster and a level-3 cache shared across up to four clusters, alongside doubled memory bandwidth. (sifive.com) ### Where does SiFive expect the P570 Gen 3 to be used? SiFive said the core can serve either as a control processor in embedded IoT devices running full networking stacks or as the main applications processor in consumer devices running Android or enterprise Linux. The company said the vector unit is meant to run AI models and inference on edge devices. (sifive.com) A separate SiFive blog post on May 12 said the company sees use cases including SmartNICs and robotics orchestration. In that post, SiFive executive Jack Kang said customers want programmable compute alongside fixed-function accelerators so systems can handle workloads that NPUs do not address well and coordinate data movement into and out of those accelerators. (sifive.com) ### Why do AIA, WorldGuard and the IOMMU matter in this announcement? SiFive said the P570 Gen 3 launch is not only about the CPU core but also about surrounding system IP. The company said it is pairing the core with a RISC-V-compliant Advanced Interrupt Architecture, WorldGuard for trusted execution environments on secure SoCs, and a second-generation RISC-V-compliant IOMMU. (sifive.com) The WorldGuard proposal in the RISC-V tech hub describes extensions intended to let a hart assign protection identifiers across privilege modes, while the RISC-V IOMMU is designed to provide device-side address translation and isolation. SiFive’s emphasis on those blocks tracks its pitch for secure, Linux-capable SoCs running mixed application and AI workloads at the edge. (sifive.com) ### How far can a P570 Gen 3 subsystem scale? SiFive said the P570 Gen 3 can scale to 16 cores in a compute subsystem. The same announcement said the shared-cache design can span up to four clusters, with up to four cores per cluster. (sifive.com) SiFive’s next step is documentation and customer design work rather than a retail chip launch. The company on May 12 pointed developers and chipmakers to its press materials, product pages and engineering blog posts for deeper architectural details on the P570 Gen 3 and the related P550 Gen 3 family. (sifive.com) (lf-riscv.atlassian.net)