New partnerships and a US SubFAB emerge

Applied Materials and Advantest said on April 21 they are linking process development and chip testing through Applied’s EPIC platform in Silicon Valley. (advantest.com) Advantest said it is the first automated test equipment company to join EPIC, and its new Innovation Center will connect with Applied Materials’ EPIC Center when that site opens later in 2026. (advantest.com) The companies said the partnership is aimed at chips used in artificial intelligence and high-performance computing, where packaging and test have become harder as more functions are stacked into one package. (advantest.com) A separate April 21 memorandum paired International SubFAB Research Labs, or ISRL USA, with AI Infrastructure Partners to build what they called the first U.S. facility dedicated to subfab research and development. (aiipartners.ai) (markets.businessinsider.com) Subfab is the utility layer under a chip fab cleanroom that handles vacuum pumps, gas treatment and chemical waste. ISRL USA said the planned site would reproduce factory conditions and give members access at less cost than a private pilot line priced above $100 million. (aiipartners.ai) ISRL USA said AI Infrastructure Partners would design, build and own the facility, while ISRL USA would run the technical programs. The companies said site selection is underway and operational readiness is targeted within 12 months of full funding. (aiipartners.ai) Another piece of the same buildout is advanced packaging, the back-end step that turns finished chips into usable modules. Resonac said in July 2024 that it formed the 10-company US-JOINT consortium in Union City, California, with Azimuth among the partners. (resonac.com) Resonac said the Union City center would house cleanrooms for packaging research and become fully operational in 2025. The consortium includes Azimuth, KLA, Kulicke & Soffa, ULVAC, TOWA and other U.S. and Japanese materials and equipment companies. (resonac.com) The talent side moved too. The Electronics Sector Skills Council of India, or ESSCI, said this week that it signed a memorandum with Synopsys International to run bootcamps, faculty programs, hackathons and joint certifications in chip design. (timestech.in) Taken together, the announcements map onto four bottlenecks in the chip business: design talent, packaging, testing and factory infrastructure. The common thread is shared development capacity closer to customers, instead of each company building every toolchain on its own. (advantest.com) (aiipartners.ai) (resonac.com)