TSMC raises 3nm and 2nm output 20%
- Taiwan Semiconductor Manufacturing Co. is reportedly lifting its 2026 3-nanometer output target to 180,000 wafers a month and accelerating 2-nanometer production. - TrendForce said TSMC’s 3nm monthly output was about 120,000 to 130,000 wafers at end-2025 and could top 180,000 by end-2026. - Packaging, testing and assembly still constrain AI chip supply after wafer output rises. (hbr.org)
Taiwan Semiconductor Manufacturing Co. is reportedly raising its 2026 output targets for 3-nanometer and 2-nanometer chips as AI demand keeps advanced capacity tight. (trendforce.com) (wccftech.com) TrendForce, citing Economic Daily News and supply-chain sources, reported on April 27 that TSMC’s Taiwan 3nm fabs are now projected to reach about 180,000 wafers a month by the end of 2026, up from an earlier 150,000 target. (trendforce.com) The same report said 3nm monthly output was around 120,000 to 130,000 wafers at the end of 2025, which implies growth of more than 40% by the end of 2026. It also said 2nm capacity could approach 100,000 wafers a month by late 2026. (trendforce.com) TSMC’s own first-quarter 2026 results, published April 16, showed why the company is pushing harder. Revenue reached $35.90 billion, gross margin hit 66.2%, and second-quarter revenue guidance rose to $39.0 billion to $40.2 billion. (investor.tsmc.com) The company said 2nm is already in production, and industry reports say AI processors, high-performance computing chips and smartphone silicon are absorbing leading-edge supply faster than older planning assumptions expected. (investor.tsmc.com) (trendforce.com) A wafer is only the starting point. After circuits are etched onto silicon, chips still need to be cut, tested and packaged into final products that can be installed in servers, graphics cards or phones. (cnbc.com) (hbr.org) That back-end work is where the next squeeze sits. CNBC reported on April 8 that Nvidia has reserved the majority of TSMC’s most advanced packaging capacity, especially for Chip-on-Wafer-on-Substrate, or CoWoS, the method used to combine logic chips with high-bandwidth memory for AI systems. (cnbc.com) Harvard Business Review wrote on April 28 that testing, packaging and assembly remain concentrated in Asia even after the United States poured money into front-end fabrication. That leaves the supply chain exposed even if wafer starts increase. (hbr.org) TSMC is also spreading future 3nm production beyond Taiwan. TrendForce said a new Southern Taiwan fab is expected to enter mass production in the first half of 2027, Arizona Fab 2 in the second half of 2027, and Kumamoto Fab 2 in 2028. (trendforce.com) The immediate story is straightforward: TSMC is trying to make more of the world’s most advanced chips, faster. The harder part is turning those wafers into finished AI hardware before packaging capacity runs out. (trendforce.com) (cnbc.com)