NVIDIA splits Feynman foundry sourcing
- Nvidia is reportedly planning a split manufacturing strategy for its 2028 Feynman AI GPUs, with TSMC keeping the main compute die while Intel Foundry supplies some chiplets and packaging. - The reported mix uses Intel’s 18A or 14A process for parts such as the I/O die, plus Intel EMIB packaging for as much as 25% of output. - The arrangement would ease Nvidia’s reliance on TSMC’s crowded advanced-packaging lines for AI chips. (notebookcheck.net)
Modern AI chips are built from several smaller dies in one package, not one giant slab of silicon. Nvidia is reportedly planning to split that work for its 2028 Feynman GPUs between Taiwan Semiconductor Manufacturing Co. and Intel Foundry. (notebookcheck.net) (techpowerup.com) The report says TSMC would still make the main compute die, which is the part that does most of the math. Intel would handle some secondary silicon, including an input-output die, on its 18A or 14A process nodes. (techpowerup.com) (hothardware.com) Packaging is the step that wires those dies and memory stacks together into one working product. The same report says Nvidia wants Intel’s Embedded Multi-die Interconnect Bridge, or EMIB, for up to 25% of Feynman packaging, with TSMC handling the rest through CoWoS. (hothardware.com) (fool.com) EMIB is Intel’s bridge-based method for linking chiplets inside one package without using a full silicon interposer. Intel says the technology is already in high-volume manufacturing and can connect logic dies and high-bandwidth memory. (intel.com) CoWoS is TSMC’s packaging platform for putting large logic chips beside stacks of high-bandwidth memory on an interposer. TSMC says CoWoS is built for high-performance computing and artificial intelligence systems, including packages larger than twice a reticle. (tsmc.com 1) (tsmc.com 2) Nvidia has already told investors and customers that Feynman is the architecture after Rubin on its data-center roadmap. Industry coverage of GTC roadmaps places Feynman in 2028, which matches the timing in the foundry report. (nextplatform.com) (techpowerup.com) The pressure point is not just wafer supply but packaging capacity. TSMC’s CoWoS lines have become a bottleneck for AI accelerators, and Intel has been expanding its own advanced-packaging pitch around EMIB and newer EMIB-T variants. (tsmc.com) (intel.com) Neither Nvidia nor Intel announced this arrangement publicly in the materials reviewed here, so the Feynman sourcing plan remains a report, not a confirmed contract. But if it holds, Nvidia would be buying more than wafers from Intel; it would be buying a second path to assemble its most important AI chips. (notebookcheck.net) (techpowerup.com)
