TSMC bets on packaging, delays costly EUV

- TSMC announced plans to open a chip-packaging plant in Arizona and unveiled a manufacturing roadmap through 2029. - The company will open the Arizona packaging plant by 2029 while holding off on ASML's high-NA EUV adoption through 2029. - That prioritises advanced packaging and capital discipline over rapid EUV rollout, reshaping chip supply-chain timing and geography. (reuters.com) (bloomberg.com)

TSMC says it will add advanced chip packaging in Arizona by 2029 and keep skipping ASML’s newest lithography machines in mass production through 2029. (money.usnews.com) (theedgesingapore.com) At TSMC’s North America Technology Symposium in Santa Clara on April 22, deputy co-chief operating officer Kevin Zhang said construction had begun in Arizona and the company aimed to build CoWoS and 3D-IC packaging there before 2029. CoWoS and 3D-IC are the steps that connect multiple pieces of silicon into one finished processor package. (money.usnews.com) (tsmc.com) That matters because many artificial-intelligence chips are no longer one chip on one slab of silicon. Nvidia- and Apple-bound wafers made in Arizona still often have to go back to Taiwan for final packaging, according to Reuters. (money.usnews.com) TSMC also said it has no current plan to adopt ASML’s high-numerical-aperture extreme ultraviolet tools for production through 2029. Zhang said the company can still get gains from existing extreme ultraviolet machines and called the next generation “very, very expensive.” (theedgesingapore.com) Those high-NA EUV systems are the giant optical tools used to print ever-smaller features on chips, and Bloomberg reported they cost more than €350 million apiece. TSMC has bought a small number for research, but not for high-volume manufacturing. (theedgesingapore.com) Instead, TSMC used the symposium to extend its roadmap with A13 entering production in 2029, while keeping its packaging push alongside its logic-node push. TSMC’s symposium agenda highlighted both transistor scaling and 3DFabric packaging as core parts of the company’s plan. (theedgesingapore.com) (tsmc.com) Arizona is already central to that buildout. TSMC said on March 4, 2025 that it intended to lift its total U.S. investment to $165 billion, including three new fabrication plants, two advanced packaging facilities and a major research-and-development center in Phoenix. (pr.tsmc.com) Other companies are moving faster on the same bottleneck. Reuters reported that Amkor said last year it was working with Apple and Nvidia on an Arizona packaging plant targeted for mid-2027 completion and early-2028 production, ahead of TSMC’s own 2029 timeline. (money.usnews.com) (manufacturingdive.com) ASML has told investors its high-NA tools should reach high-volume production in 2027 and 2028, and Bloomberg said ASML’s U.S.-traded shares fell as much as 5.5% after TSMC’s comments. TSMC’s capital spending could approach $56 billion in 2026, which helps explain why it is stretching more output from older EUV gear before buying more of the newest machines. (theedgesingapore.com) The result is a slower timetable for bringing the last step of advanced chipmaking to the U.S., even as Arizona adds more wafer capacity. TSMC is still expanding in America, but its April 22 message was that packaging gets the next big push before the most expensive lithography does. (money.usnews.com) (theedgesingapore.com)

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