TSMC packaging bottleneck

Taiwan Semiconductor Manufacturing Co. is making plenty of chips for the artificial intelligence boom. The harder part now is finishing them. (investor.tsmc.com) That finishing step is called advanced packaging: it connects several small chips and stacks high-bandwidth memory into one processor package. TSMC’s main version, Chip on Wafer on Substrate, is built for artificial intelligence and supercomputing chips. (tsmc.com) On April 8, CNBC reported that Nvidia had reserved the majority of TSMC’s most advanced packaging capacity. TSMC packaging executive Paul Rousseau told the network demand is growing “very substantially,” and said Chip on Wafer on Substrate capacity is rising at an 80% compound annual growth rate. (cnbc.com) TSMC’s first-quarter 2026 investor page shows the company guiding revenue to $34.6 billion to $35.8 billion, with gross margin of 63% to 65% and operating margin of 54% to 56%. The earnings call is scheduled for April 16, 2026, after a quiet period that began April 6. (investor.tsmc.com) The squeeze is shifting from the front end of chipmaking to the back end. A company can secure a leading-edge wafer and still wait for the packaging line that turns it into a usable graphics processing unit or custom artificial intelligence accelerator. (cnbc.com) That matters because today’s artificial intelligence chips are not single slabs of silicon. They are multi-chip systems that combine logic dies and high-bandwidth memory with dense wiring over a large interposer, which is a base layer that links the parts together. (tsmc.com) TSMC is adding capacity in both Taiwan and the United States. On March 4, 2025, the company said its expanded $165 billion Arizona plan would include two advanced packaging facilities, alongside three new fabrication plants and a research and development center. (pr.tsmc.com) TSMC said that Arizona expansion would raise its total planned United States investment from $65 billion to $165 billion. The company also said the Phoenix site had been in volume production since late 2024 and employed more than 3,000 people. (pr.tsmc.com) The geography matters because most advanced packaging still happens in Asia. CNBC reported that TSMC is building its first United States advanced packaging facilities in Arizona this year while ramping two new sites in Taiwan. (cnbc.com) Intel is the other major packaging player at the top end of the market, and CNBC reported that Amazon, Cisco, SpaceX, Tesla and other customers are using or planning packaging work there. That gives chip designers a second route, but it does not remove TSMC from the center of the artificial intelligence supply chain. (cnbc.com) For now, the bottleneck is not whether TSMC can etch more transistors onto a wafer. It is whether the industry can package enough of those wafers into the giant processors that data centers are ordering by the rack. (cnbc.com)