Foundry squeeze: TSMC limits
AI demand is squeezing fabs — TSMC’s 3nm capacity is constrained and CoWoS advanced packaging is running near ~75–80k wafers/month, tightening optics, PCB and packaging lead times ( ). Analysts warn China still trails by 5–10 years on AI‑chip supply chains because of fab‑equipment and talent bottlenecks, and Middle East risks are elevating lead times for specialty chemicals used in advanced packaging ( ).
Industry estimates put TSMC’s current CoWoS advanced‑packaging throughput at roughly 75,000–80,000 wafers per month. (trendforce.com) TSMC is targeting a multi‑fold scale‑up, with industry reporting the foundry’s CoWoS capacity goal at about 120,000–130,000 wafers/month by the end of 2026. (financialcontent.com) TSMC’s 3nm wafer allocation is effectively fully booked for the next 18–24 months, with lead times for 3nm slots and packaged accelerators stretching beyond 50 weeks in market trackers. (siliconanalysts.com) Market trackers show 3nm wafer pricing firming around roughly $20,000 per wafer and separate reporting suggests 2nm wafers could trade about $30,000 each, pressuring program budgets and prioritization. (siliconanalysts.com) Chinese industry leaders and independent analysts at recent trade events acknowledged a technology and supply‑chain gap of about five to ten years on high‑end AI and data‑center chips, citing equipment access and skilled‑talent shortfalls. (nature.com) Analysts and ratings firms warn the Middle East conflict is tightening supply of chemical feedstocks—naphtha, LPG and methanol—and specialist gases such as helium, raising lead times and insurance/logistics costs for packaging materials. (fitchratings.com) The capacity squeeze is driving a secondary response: OSATs and substrate makers are scaling, while industry chokepoint maps flag concentrated suppliers (for example, ABF substrate film and other materials remain highly concentrated), creating parallel pressure on PCB, optics and packaging lead times. (trendforce.com)
