Apple Unveils M5 Chip, MacBook Neo
Apple just launched the MacBook Neo, powered by its new M5 chip. The M5 is being positioned as a win in the AI race, with a new neural engine and ML co-processors focused on on-device AI tasks and industry-leading energy efficiency. This tight integration of custom silicon and software sets a new benchmark for performance-per-watt in AI-native hardware.
The M5 chip likely advances on the second-generation 3-nanometer process (N3E) used for the M4, pushing toward TSMC's next manufacturing node. This progression is critical for increasing transistor density beyond the M4's 28 billion, which directly impacts computational throughput and power efficiency—key metrics in ASIC design. Apple's Neural Engine has seen exponential growth, from 600 billion operations per second in the 2017 A11 Bionic chip to 38 trillion (TOPS) in the M4. The M5's new engine is central to its on-device AI focus, providing the performance required for complex robotics and autonomous system workloads, which rely on low-latency, local inference rather than cloud processing. The entire M-series project is spearheaded by Johny Srouji, Apple's SVP of Hardware Technologies, who joined in 2008 to lead the development of the A4 chip. His team's strategy of vertical integration gives Apple full control over hardware and software, a significant advantage over competitors who rely on more fragmented supply chains for AI accelerators. Historically, Apple's chip generations have shown significant gains; the M3's performance cores were up to 30% faster than the M1's, and its efficiency cores were 50% faster. The M4 continued this trend, offering CPU performance up to 1.8 times faster than the M1, setting high expectations for the M5's performance in tasks like compiling large codebases and running complex simulations. The push for on-device AI places the M5 in direct competition with custom silicon from companies like Qualcomm, which uses its Hexagon NPU, and Google's Tensor Processing Units (TPUs). This industry-wide shift toward specialized hardware accelerators is a core trend for embedded systems, prioritizing efficient machine learning on battery-powered devices. A key architectural advantage for Apple is its Unified Memory Architecture (UMA), which provides a single pool of high-bandwidth memory accessible by the CPU, GPU, and Neural Engine. The M4 Max offered up to 546 GB/s of bandwidth, eliminating the need to copy data between separate memory pools and drastically reducing latency for real-time processing tasks.
