TSMC expands in Arizona
- TSMC plans to open a chip packaging plant in Arizona by 2029, adding downstream semiconductor capacity in the U.S. - The company also debuted an A13 technology roadmap and said it can make smaller, faster chips without ASML’s pricier next‑generation tool. - The announcement highlights that reshoring requires adjacent capabilities like packaging, testing, and long‑dated capital investments to reduce supply risk. (reuters.com) (reuters.com)
A semiconductor fab makes the silicon wafer, but the chip still needs to be cut, stacked, wired, tested, and sealed before it can ship. Taiwan Semiconductor Manufacturing Co. said on April 22 it plans to add that packaging step in Arizona with a new plant targeted for 2029. (reuters.com) The plant would extend TSMC’s Phoenix site beyond wafer production into the downstream work that turns finished wafers into usable processors. Reuters reported the company gave the 2029 target at its North America technology symposium in Santa Clara, California, on April 22. (reuters.com) TSMC already has three Arizona fabs in motion. Its first Arizona fab entered volume production of 4-nanometer chips in the fourth quarter of 2024, the second is being outfitted for 3-nanometer production, and the third fab broke ground in April 2025 for N2 and A16 technologies later in the decade. (investor.tsmc.com) (tsmc.com) The Arizona buildout has grown fast. TSMC said in March 2025 it intended to expand its total U.S. investment to $165 billion, up from the earlier $65 billion Arizona plan tied to three fabs. (pr.tsmc.com) Packaging has become a bottleneck because advanced chips now arrive in pieces that must be combined like a compact electronics stack, not just printed on one slab of silicon. TSMC’s own roadmap now treats packaging as part of system design through technologies such as CoWoS, InFO, SoIC, and System-on-Wafer for artificial intelligence and high-performance computing customers. (tsmc.com 1) (tsmc.com 2) TSMC used the same April 22 symposium to show where the wafers themselves are headed. The company debuted an A13 process, said it is a direct shrink of A14, and said A13 is scheduled for production in 2029 with 6% area savings over A14 plus gains in power efficiency and performance. (pr.tsmc.com) That roadmap also touched a costly tool question hanging over the industry. Reuters reported TSMC said it can keep scaling chips without relying on ASML’s newer High NA extreme ultraviolet machines, which are designed to print smaller features with a larger 0.55 numerical aperture. (reuters.com) (asml.com) ASML says its High NA EXE platform can print 1.7-times-smaller features than earlier EUV systems and support future 2-nanometer-class manufacturing. TSMC’s position suggests it sees enough room in existing EUV tools, process tweaks, and design changes to reach A14 and A13 without moving immediately to the pricier platform. (asml.com 1) (asml.com 2) (pr.tsmc.com) The Arizona announcement puts those two pieces together: the wafer line and the finishing line. By 2029, if TSMC meets its timetable, Phoenix would be making advanced chips and packaging more of them in the same state instead of sending that work back across the Pacific. (reuters.com) (tsmc.com)
