New Metrology Technique Advances GAA Chip Manufacturing
A new process control method for Gate-All-Around (GAA) transistors was presented at the SPIE Advanced Lithography Conference in San Jose. The technique allows for estimating the crystal heights of GAA devices from 2D SEM images, enabling real-time, in-line monitoring to improve yield and performance for sub-3nm nodes.
- Gate-All-Around (GAA) architecture is the successor to the FinFET transistor design used in recent chip generations; it improves performance and reduces power leakage by wrapping the gate around all four sides of the channel, a critical step for manufacturing at 3nm and below. - Samsung was the first to begin high-volume manufacturing of GAA-based chips with its 3nm process in June 2022, claiming its first-generation process could cut power use by 45% and improve performance by 23% compared to its 5nm process. However, reports in late 2024 indicated that yields for its second-generation 3nm process were as low as 20%, well below the 70% target. - Competitor TSMC is introducing its version of GAA, called nanosheet technology, with its 2nm (N2) node, which began volume production in late 2025. TSMC's N2 process is projected to deliver a 10-15% speed increase at the same power or a 25-30% power reduction at the same speed compared to its N3E node. - Intel is implementing its GAA variant, named RibbonFET, in its "Intel 20A" process, which is scheduled for the first half of 2024. This will be followed by "Intel 18A" in early 2025, which pairs RibbonFET with a backside power delivery network called PowerVia to further boost performance and transistor density. - Manufacturing GAA transistors presents significant metrology challenges due to their complex, three-dimensional structures and angstrom-level precision requirements. Traditional optical and SEM-based measurement techniques struggle to characterize buried features and control process variations, making new in-line monitoring methods essential for improving production yields. - The SPIE Advanced Lithography + Patterning conference is a key industry forum where academic and corporate researchers present solutions to major manufacturing hurdles. Innovations in metrology, computational patterning, and EUV lithography are discussed here to enable next-generation nodes. - The transition to sub-3nm nodes using GAA requires advancements in Extreme Ultraviolet (EUV) lithography and introduces new potential issues like quantum tunneling and increased heat dissipation that must be managed.
