GAA FETs, High‑NA EUV push node density
- TSMC used its April 22 technology symposium to show A13, a next-step logic process that shrinks designs beyond A14, while Intel and ASML keep pushing gate-all-around transistors and High-NA tools into production. - ASML says its High-NA EXE:5000 can print 1.7-times-smaller features and support 2.9-times-higher transistor density than earlier EUV systems, while TSMC says N2 entered volume production in fourth-quarter 2025. - The race has shifted from FinFET scaling alone to nanosheet transistors, backside power and new lithography, with complementary-field-effect transistor research already lining up the next step. (asml.com) (tsmc.com)
Chipmakers are now changing both the transistor and the printing tool to keep packing in more logic. TSMC, Intel and ASML are all moving beyond the old FinFET playbook. (tsmc.com) (intel.com) (asml.com) A transistor is the on-off switch inside a chip. Gate-all-around designs wrap the switch’s gate around the channel on more sides than FinFETs, which helps cut leakage as features get smaller. (intel.com) (tsmc.com) TSMC says its 2-nanometer N2 process uses first-generation nanosheet transistors, its version of gate-all-around, and started volume production in the fourth quarter of 2025. The company says N2P follows in the second half of 2026. (tsmc.com) TSMC’s research arm says N2 offers a 15% speed gain or 30% power reduction from its prior 3-nanometer node, with more than 1.15-times chip density increase and SRAM density around 38 megabits per square millimeter. (tsmc.com) Intel is making the same transistor shift with RibbonFET, its gate-all-around design, on the 18A node. Intel says 18A is ready for customer projects and brings up to 15% better performance per watt and 30% better chip density than Intel 3. (intel.com) Intel pairs RibbonFET with PowerVia, which moves power wiring to the back of the wafer instead of the front. Intel says that backside-power approach improves standard-cell utilization by 5% to 10% and lifts iso-power performance by up to 4%. (intel.com) The printing tool is changing too. ASML’s High-NA extreme ultraviolet machine, the EXE:5000, uses 0.55 numerical aperture optics and 8-nanometer resolution to print smaller features in a single exposure. (asml.com) ASML says that jump lets chipmakers print features 1.7 times smaller and reach transistor densities 2.9 times higher than with its earlier NXE EUV systems. The company says the EXE platform is aimed at high-volume manufacturing in 2025 and 2026, starting with 2-nanometer-class logic. (asml.com 1) (asml.com 2) TSMC used its April 22, 2026 North America Technology Symposium to show how fast that roadmap is moving. It introduced A13 as a direct shrink of A14, with 6% area savings from A14 and production scheduled for 2029. (tsmc.com) At the same event, TSMC said it is previewing A12 with backside power delivery and adding N2U, a 2028 extension of its 2-nanometer platform. TSMC says N2U targets 3% to 4% speed gains or 8% to 10% lower power than N2P, plus a modest logic-density lift. (tsmc.com) The next transistor after gate-all-around is already in research labs. TSMC says it demonstrated a monolithic complementary field-effect transistor inverter at 48-nanometer gate pitch, stacking n-type and p-type devices vertically to save area. (tsmc.com) A separate line of research is testing different logic altogether. A Nature Communications paper published April 11, 2026 described a CMOS-compatible array that combines probabilistic bits and synapses on one wafer to solve weighted max-cut problems, pointing to low-power hardware beyond conventional scaling. (nature.com) The near-term map is clear: nanosheet transistors are in production, backside power is moving into product roadmaps, and High-NA EUV is being positioned for 2-nanometer-class manufacturing. The harder part now is who can afford the tools, yields and design changes needed to use them at scale. (tsmc.com) (intel.com) (asml.com)
