TSMC to add U.S. packaging, delay high‑NA EUV

TSMC plans to open a chip-packaging plant in Arizona by 2029, extending its U.S. buildout beyond wafer fabrication and into a step that has become critical for artificial intelligence chips. (reuters.com) Packaging is the stage after a chip is manufactured, when multiple pieces of silicon and memory are combined into one finished part. Reuters reported on April 22 that TSMC’s Arizona site is targeting that capability by 2029 after the company said in January it was seeking permits for its first advanced packaging plant there. (reuters.com) That step matters because many AI processors from Nvidia and others are no longer single chips; they are several chiplets joined together with advanced packaging. Reuters said that backend assembly has become a supply bottleneck for Nvidia and other customers. (reuters.com) At the same event in Santa Clara, TSMC said it has no current plan to use ASML’s high-numerical-aperture extreme ultraviolet machines in production through 2029. Bloomberg reported those tools cost more than €350 million, or about $410 million, each. (bloomberg.com) High-NA EUV is the newest version of the light-based patterning equipment used to print tiny circuit features onto wafers. Intel said in April 2024 that it had completed installation of the first commercial High-NA EUV system at its Oregon development fab, showing a different timetable from TSMC’s. (intel.com) Instead of moving first on that tool set, TSMC used its 2026 North America Technology Symposium to introduce A13, its next leading-edge process. TSMC said A13 is a direct shrink of A14, with 6% area reduction, up to 15% speed gain at the same power, or 30% lower power at the same speed, and it is scheduled for production in 2029. (tsmc.com) TSMC also outlined N2U, a later version of its 2-nanometer platform aimed at customers that want lower risk and lower cost than a full jump to a new node. The company said N2U is scheduled for production in 2028 and offers 3% to 4% higher speed or 8% to 10% lower power than N2P. (tsmc.com) The Arizona packaging plan fits a much larger U.S. expansion. TSMC said on March 4, 2025 that it intended to raise its U.S. investment to $165 billion, adding three new fabs, two advanced packaging facilities, and a research and development center in Arizona. (tsmc.com) Reuters reported last week that TSMC had completed construction of its second Arizona fab and expected volume production there in the second half of 2027, while the third fab was still targeted for the end of the decade. The packaging plant would fill in a missing piece between wafer output and finished AI processors. (usatoday.com; reuters.com) TSMC’s message on April 22 was that it will keep expanding in the United States, but it will not buy every new tool as soon as it appears. The company is adding packaging in Arizona, steering customers toward A13 and N2U, and leaving High-NA EUV for later. (reuters.com; bloomberg.com; tsmc.com)