Packaging demand: HBM4 squeeze
High‑bandwidth memory demand is surging — the briefing flags Nvidia’s need for as many as 10 million HBM4 modules and says only four suppliers are in the mix, creating a tight supply picture (x.com). The same notes show CoWoS assembly growing ~80% and Nvidia locking more than 50% of capacity into 2027, while TSMC is scaling toward ~130,000 wafers per month to meet demand — all signs that packaging and test, not just wafer fab, are real chokepoints ( ).
The bottleneck in artificial intelligence chips is no longer just making the compute die. It is also the step where the chip gets surrounded by stacks of memory and then stitched into one package, and Taiwan Semiconductor Manufacturing says its Chip-on-Wafer-on-Substrate line is still expanding fast because demand keeps outrunning supply. (tsmc.com; trendforce.com) High Bandwidth Memory is the memory used beside top-end artificial intelligence processors because it moves far more data than ordinary server memory by stacking dynamic random-access memory chips vertically and connecting them with tiny vertical wires. SK hynix says High Bandwidth Memory 4 is its next-generation product for artificial intelligence, and Samsung says its commercial High Bandwidth Memory 4 has transfer speeds up to 13 gigabits per second. (skhynix.com; samsung.com) That memory is useless until it is physically attached close to the processor inside one advanced package. Taiwan Semiconductor Manufacturing’s Chip-on-Wafer-on-Substrate process does that job, and the company says its next 9.5-reticle-size version will let one package hold 12 or more High Bandwidth Memory stacks starting in 2027 volume production. (tsmc.com) That is why packaging has turned into its own supply crisis. TrendForce reported that Taiwan Semiconductor Manufacturing’s monthly Chip-on-Wafer-on-Substrate capacity was projected around 70,000 wafers by the end of 2025, while later industry estimates cited by TrendForce put the end-of-2026 target at roughly 120,000 to 130,000 wafers per month. (trendforce.com; trendforce.com) Even that buildout may not clear the line. TrendForce said demand for Chip-on-Wafer-on-Substrate significantly exceeded Taiwan Semiconductor Manufacturing’s ability to supply even after capacity doubled year over year in 2024 and 2025, and delivery schedules for equipment were already essentially full. (trendforce.com) Nvidia sits in the middle of this because its Blackwell and Rubin accelerators need both the compute chip and the memory stacks to arrive at the packaging line at the same time. TrendForce reported in March 2026 that Samsung Electronics and SK hynix were on Nvidia’s supplier list for Rubin High Bandwidth Memory 4, and it added that making High Bandwidth Memory 4 takes more than six months from dynamic random-access memory wafer to final packaging. (trendforce.com) The supplier pool is narrow even before the package reaches Taiwan Semiconductor Manufacturing. Publicly confirmed High Bandwidth Memory 4 makers are SK hynix and Samsung, Micron has been advancing its High Bandwidth Memory roadmap, and the packaging side still depends heavily on Taiwan Semiconductor Manufacturing and a small group of outsourced assembly and test companies stepping in around it. (skhynix.com; samsung.com; trendforce.com) That is why outsourced assembly and test companies are suddenly part of the artificial intelligence story. TrendForce reported that Powertech had developed technology competing with Taiwan Semiconductor Manufacturing’s Chip-on-Wafer-on-Substrate-L and won multiple United States artificial intelligence chip orders, with most of its advanced packaging capacity for 2026 already taken. (trendforce.com) Geography makes the squeeze tighter. TrendForce reported in June 2025 that Nvidia chips produced at Taiwan Semiconductor Manufacturing’s Arizona fab still had to be shipped back to Taiwan for advanced packaging because United States packaging capacity was not ready yet. (trendforce.com) So when investors look at artificial intelligence chip supply, the limiting machine is not always the lithography scanner in the wafer fab. It can be the packaging line that has to combine one logic die, a dozen memory stacks, and final test capacity into a single finished part, and Taiwan Semiconductor Manufacturing’s own roadmap now treats that stage as a factory-scale expansion problem through 2027. (tsmc.com; trendforce.com)
