Siemens Uses Agentic AI for Chip Design
Siemens announced the deployment of agentic AI within its Questa One platform to accelerate the design and verification of integrated circuits. The system uses AI agents with specific domain knowledge, combined with configurable human expertise, to speed up the register-transfer level (RTL) sign-off process in semiconductor development.
The new Questa One Agentic Toolkit is part of a broader, purpose-built "Fuse EDA AI" system from Siemens that integrates both generative and agentic AI across its entire electronic design automation (EDA) portfolio. This strategic push aims to embed AI as a core function in the semiconductor design process, moving it from a peripheral enhancement to a central enabler of innovation. The system leverages a centralized data lake to break down silos between design teams and utilizes natural language interfaces to automate tasks. This agentic AI approach directly targets the time-intensive verification and debugging stages of chip design. The toolkit includes five distinct AI agents: an RTL Code Agent for generating code, a Lint Agent for error checking, a CDC Agent for clock domain crossing verification, a Verification Planning Agent, and a Debug Agent for analyzing failures. These agents work autonomously to handle tasks that previously required significant manual engineering effort, addressing a critical shortage of chip design expertise. The Register-Transfer Level (RTL) sign-off is a critical bottleneck where design flaws identified late can force costly and time-consuming revisions. Issues like clock domain crossings (CDC) and reset domain crossings (RDC) are major risks that can necessitate a complete respin of the silicon if not caught early. By "shifting left" and applying AI-powered analysis at the RTL stage, the goal is to fix as many issues as possible before they propagate downstream. Siemens is collaborating with NVIDIA, using its NIM and Nemotron models to power the new AI-driven workflows. This partnership highlights a growing trend of EDA vendors embedding AI into their core tools. Early adopters like MediaTek have reported that engineers became proficient with the new toolkit within hours, noting "immediate and significant" productivity gains. This rapid onboarding is crucial for addressing the industry's talent gap. The broader industry context is a race to manage skyrocketing design complexity and reduce time-to-market for next-generation chips. Projections suggest that by 2027, up to 90% of advanced chips will be designed using agentic AI. This shift is seen as being as transformative to the industry as the move from manual drafting to computer-aided design (CAD) tools decades ago.
