Trading Firms Push FPGAs to the Edge
Top trading firms are deepening their reliance on FPGAs for ultra-low-latency execution. Nasdaq is highlighting its proprietary in-house stack for deterministic order management, while Optiver is sharing its playbook on balancing speed with operational risk. The consensus is that offloading critical path functions like risk checks to hardware is now a core design principle for HFT.
The pivot to hardware isn't new; firms began leveraging FPGAs for market data processing back in 2007. What has changed is the scope of their deployment. Initially used to accelerate ticker plant performance, FPGAs are now being tasked with transactional roles, including order entry and pre-trade risk, shrinking the entire tick-to-trade loop to hundreds of nanoseconds. FPGAs provide a crucial advantage in their deterministic latency. Unlike CPUs, which are subject to operating system interrupts and context switching, FPGAs execute logic in parallel directly on the silicon. This eliminates jitter and ensures the same function takes the same number of clock cycles every time, a critical factor when market opportunities vanish in microseconds. Major proprietary trading firms and market makers like Jump Trading, Citadel Securities, and IMC Trading have integrated FPGAs into their core infrastructure. Jump Trading, for instance, utilizes FPGAs and custom silicon to achieve end-to-end trade execution latency as low as 90 microseconds. Optiver has made hardware a strategic pillar, using FPGAs to manage complexity across thousands of instruments and multiple venues in real-time. This hardware acceleration extends beyond just speed to encompass the entire trading pipeline. FPGAs can directly ingest and parse exchange data feeds like NASDAQ's ITCH and OUCH protocols in hardware, with open-source parsers achieving sub-25 nanosecond latency. This allows for filtering and pre-processing of market data at network speeds before it even reaches a CPU. The evolution of FPGA technology now sees hybrid architectures becoming more common. In these systems, FPGAs handle the most latency-sensitive tasks—market data parsing, order book management, and risk checks—while CPUs manage more complex strategy formulation and analytics. This allows firms to balance the raw performance of hardware with the flexibility of software. Looking ahead, the accessibility of FPGAs is increasing. High-level synthesis (HLS) tools that can generate hardware designs from C++ or Python are making the technology more approachable for software engineers. This trend, combined with the increasing use of FPGAs for machine learning applications in trading, points to a future where configurable silicon is a foundational element of low-latency infrastructure.
