TSMC advances packaging pilot
TSMC says it is advancing panel‑level packaging with a CoPoS pilot line reportedly due for completion in June, aiming for a commercial ramp in 2028–29. The announcement comes as TSMC is expected to post another record quarter on strong AI demand and as advanced-node and CoWoS capacity appear heavily utilised into 2027. These moves point to packaging and testing throughput becoming critical constraints alongside pure wafer capacity. (www.trendforce.com (reuters.com)
Taiwan Semiconductor Manufacturing Co. is pushing a new chip-packaging pilot toward June completion as it races to ease an artificial intelligence supply choke point. (trendforce.com) The pilot uses Chip-on-Panel-on-Substrate, or CoPoS, a method that swaps the industry’s usual round wafer-like base for a larger rectangular panel. TrendForce, citing Commercial Times, said tools started reaching research teams in February and the full pilot line is due to be finished in June. (trendforce.com) TrendForce reported TSMC is targeting commercial production in 2028 or 2029. Earlier reports tied the pilot to TSMC’s VisionChip unit and mass production to the company’s Chiayi advanced-packaging site. (trendforce.com) (techpowerup.com) Chip packaging is the assembly step that wires silicon, memory and connections into one finished module after the chips are made. For artificial intelligence processors, that step has become as important as the wafer fab because systems now combine multiple compute dies with high-bandwidth memory in one package. (tsmc.com) (anysilicon.com) TSMC’s current workhorse for that job is Chip-on-Wafer-on-Substrate, or CoWoS, which the company says is used for ultra-high-performance computing products including artificial intelligence and supercomputing. In its 2024 annual report, TSMC said CoWoS-S had been in volume production for several years, while CoWoS-R entered its second year of volume production in 2024 and CoWoS-L started volume production in 2024. (tsmc.com) (investor.tsmc.com) The pressure is showing up in TSMC’s numbers. Reuters reported on April 13 that analysts expected a fourth straight record quarter, with January-to-March net profit seen rising about 50% on demand for artificial intelligence infrastructure. (money.usnews.com) TSMC has already told investors that advanced packaging is one of the technologies pulling growth higher. In its 2024 annual report, the company said strong demand for leading-edge logic and advanced packaging helped lift 2024 revenue 30% year over year in U.S. dollar terms. (investor.tsmc.com) The company is also still spending heavily on core manufacturing. TSMC’s investor relations page for fourth-quarter 2025 results shows first-quarter 2026 revenue guidance of $34.6 billion to $35.8 billion and a 2026 capital budget of $52 billion to $56 billion. (investor.tsmc.com) The packaging shift is about size and throughput. Reports on CoPoS have described square panels around 310 millimeters by 310 millimeters, a format meant to fit larger artificial intelligence packages more efficiently than circular wafers. (techpowerup.com) (trendforce.com) If the June milestone holds, TSMC will spend the next two to three years turning a research line into a factory process. That leaves packaging, testing and final assembly on the same critical path as leading-edge wafer output for the next wave of artificial intelligence chips. (trendforce.com) (investor.tsmc.com)
