Samsung Ships HBM4 Memory Chips
Samsung has begun commercial shipments of its HBM4 memory chips, which are designed for the next generation of AI accelerators. The new chips offer 46% faster transfer speeds and are expected to be used in high-performance hardware such as NVIDIA's upcoming Rubin AI Accelerator.
- HBM4 represents a major architectural shift by doubling the memory interface width from 1024 bits in HBM3E to 2048 bits. This change boosts the total memory bandwidth per stack by 2.7 times compared to its predecessor, reaching up to 3.3 terabytes-per-second (TB/s). - Samsung is using advanced manufacturing processes for HBM4, combining its 6th-generation 1c DRAM with a 4nm logic process for the base die, which controls the memory stack. This integration is also designed to improve power efficiency by 40% over HBM3E. - Beyond the initial 12-layer stacks offering 24GB to 36GB capacities, Samsung plans to introduce 16-layer stacking technology, which will enable modules with up to 48GB of capacity. - Both of Samsung's main competitors, SK Hynix and Micron, have also entered the HBM4 market. SK Hynix has completed its HBM4 development and is preparing for mass production, while Micron announced it has also begun volume shipments, a quarter ahead of its previous schedule. - The primary initial customer for HBM4 is expected to be NVIDIA for its next-generation "Rubin" AI platform, which is slated for a 2026 release. The Rubin GPU is designed to incorporate HBM4 to achieve nearly triple the memory bandwidth of its "Blackwell" predecessor. - Due to the wider interface, HBM4 is not backward-compatible with HBM3e, requiring a complete redesign of the silicon interposer that connects the memory to the processor.
