TSMC packaging roadmap revealed
- TSMC’s North America symposium roadmap shows CoWoS scaling to a 14x reticle, aiming for 10 compute dies plus 20 HBM stacks by 2028. - The company also plans a 40x SoW‑X package target in 2029, per symposium notes circulating on social platforms. - Those packaging roadmaps indicate big, near‑term moves to densify AI compute with stacked memory and multi‑die systems. ( )
TSMC is stretching the chip package around AI processors almost as aggressively as the processors themselves, with CoWoS headed past 14 reticles in 2029. (pr.tsmc.com) At TSMC’s North America Technology Symposium in Santa Clara on April 22, 2026, the company said its CoWoS roadmap reaches 9.5 reticles in 2027 and then expands to “beyond 14 reticles” in 2029. The same symposium materials say those offerings will complement a 40-reticle SoW-X, or System-on-Wafer, technology also expected in 2029. (pr.tsmc.com, pr.tsmc.com) In plain terms, packaging is the wiring and real estate that lets one AI chip sit beside stacks of high-bandwidth memory instead of trying to squeeze everything onto one piece of silicon. TSMC’s CoWoS platform is built for that job, linking logic chiplets and HBM on a shared base with very short connections. (tsmc.com, tsmc.com) TSMC’s 2025 symposium materials had set a smaller near-term marker: 9.5-reticle CoWoS in volume production in 2027, with 12 HBM stacks or more in one package. The new 2026 roadmap pushes the public target further out, from that 2027 step-up to a package size beyond 14 reticles by 2029. (pr.tsmc.com, pr.tsmc.com, pr.tsmc.com) That shift tracks the bottleneck AI chipmakers have been hitting for two years: not just making faster compute dies, but feeding them enough memory and connecting enough chiplets in one module. TSMC said the symposium would cover “system integration” alongside transistor scaling, and its packaging roadmap puts that system work on the same timetable as new logic nodes such as A13, N2U and A12. (tsmc.com, pr.tsmc.com) CoWoS and SoW-X solve related problems at different scales. TSMC describes CoWoS as chip-on-wafer-on-substrate packaging for high-performance computing, while SoW-X is a wafer-sized system approach that the company said in 2025 could deliver 40 times the compute power of its then-current CoWoS solution. (tsmc.com, pr.tsmc.com) TSMC has not, in the public press release, spelled out the die-and-memory counts circulating from symposium notes on social platforms. What it has published is the package-size roadmap itself: 9.5-reticle CoWoS in 2027, beyond 14 reticles in 2029, and 40-reticle SoW-X also expected in 2029. (pr.tsmc.com, pr.tsmc.com) For chip designers building the next AI servers, the practical message is that the package is becoming the product. TSMC’s 2026 roadmap shows the company planning to scale the platform around the compute die, not just the die itself. (tsmc.com, pr.tsmc.com)
