Intel bets on EMIB‑T packaging
Intel is preparing to roll out its EMIB‑T advanced packaging in fabs this year as an alternative while TSMC’s CoWoS capacity stays tight, signaling Intel’s play to compete at the system‑integration and packaging layer. That move suggests customers might get more credible second‑source options for multi‑die accelerators if Intel can scale packaging and partner deals. (startupnews.fyi)
The bottleneck in artificial intelligence chips is no longer always the chip. In 2026, one of the hardest parts is packing several compute dies and stacks of high bandwidth memory into one module without slowing signals or cooking the whole thing. (intel.com) That packing step is called advanced packaging. It works like turning separate engine parts into a finished race car, because the silicon dies, memory stacks, substrate, power delivery, and cooling all have to fit together as one product. (intel.com) For the biggest artificial intelligence accelerators, many companies now avoid building one giant chip. They split the design into smaller dies, because smaller dies usually improve yield and let designers mix logic chips with high bandwidth memory in one package. (intel.com) Taiwan Semiconductor Manufacturing Company became the center of that market with Chip on Wafer on Substrate, which is its packaging method for putting large logic dies next to high bandwidth memory. Demand got so strong that industry reports in late 2025 said multiple Chip on Wafer on Substrate lines were fully booked. (trendforce.com) Intel’s answer is Embedded Multi-die Interconnect Bridge, which uses small silicon bridges buried inside the package instead of one giant silicon base under the whole design. Intel says that approach can cut silicon use and simplify assembly compared with a full interposer-style package. (intel.com) The new version is Embedded Multi-die Interconnect Bridge-T, and the “T” stands for through-silicon vias. Those are tiny vertical holes through the bridge that carry power more directly, which matters when high bandwidth memory and large logic dies are pulling huge current. (intel.com) Intel says Embedded Multi-die Interconnect Bridge-T is aimed at high-performance computing and artificial intelligence devices that are larger than a single photolithography field. Intel’s foundry group says it can support packaged systems bigger than 6 times reticle size today, more than 8 times this year, and more than 12 times by 2028. (intel.com) Intel is not pitching this as a lab demo. Its packaging page says Embedded Multi-die Interconnect Bridge has been in mass production since 2017 with both Intel silicon and external silicon, and the company now says Embedded Multi-die Interconnect Bridge-T can help customers convert designs that were built for other packaging flows. (intel.com) That is why this rollout is getting attention now. If cloud companies can buy packaging from Intel Foundry instead of waiting on Taiwan Semiconductor Manufacturing Company’s Chip on Wafer on Substrate queue, Intel starts competing at the assembly layer even when it does not make the customer’s compute die. (arstechnica.com) Wired reporting cited by several outlets this week said Intel has been in talks with Google and Amazon about packaging services for custom artificial intelligence chips. Neither deal is announced, but the talks fit Intel’s push to sell packaging as a foundry product on its own. (techspot.com) The test is not whether Intel can name a new bridge. The test is whether Intel can scale substrate supply, memory integration, thermal control, and customer support fast enough that a second source for giant multi-die accelerators feels real instead of theoretical. (intel.com)
