Packaging is the choke point
The semiconductor bottleneck has shifted from making wafers to finishing them with advanced packaging, and one buyer is hoarding the scarce capacity. Nvidia has reserved most of TSMC’s advanced CoWoS packaging while TSMC expands sites in Arizona and Taiwan, leaving other chip makers facing 12–18 month waits for equivalent capacity and keeping high-performance modules tight. That squeeze ripples across substrates, materials and test services because a wafer without packaging still can’t ship as a usable part. (cnbc.com)
A chip is not finished when the silicon comes out of the fab. For the newest artificial intelligence processors, the last step is a kind of assembly job that bolts compute chips to memory chips and routes thousands of tiny connections between them, and that assembly step is now the slowest part of the whole business. (cnbc.com) That step is called advanced packaging, and Taiwan Semiconductor Manufacturing Company does much of the world’s highest-end version. Its Chip-on-Wafer-on-Substrate process, shortened to CoWoS, is used to join graphics processors with stacks of high-bandwidth memory in one module. (cnbc.com) Nvidia has now reserved the majority of Taiwan Semiconductor Manufacturing Company’s most advanced CoWoS capacity, according to CNBC’s April 8 report. That leaves rival chip designers trying to line up equivalent packaging slots months after they have already designed and taped out their chips. (cnbc.com) The wait is not a few extra weeks. CNBC reported that companies can face 12 to 18 months before they can get comparable advanced packaging capacity, which turns packaging from a back-end factory task into a gatekeeper for who can ship high-end artificial intelligence hardware at all. (cnbc.com) This happened because the newest artificial intelligence chips are no longer one big slab of silicon. Nvidia’s Blackwell systems combine multiple compute dies with high-bandwidth memory in one package, so the package itself has become part of the performance story rather than a plastic shell around the chip. (nvidia.com) Taiwan Semiconductor Manufacturing Company is trying to add capacity fast. The company told CNBC it is expanding CoWoS at roughly an 80% compound annual growth rate, and it is building new packaging capacity in Taiwan while also planning its first advanced packaging facilities in Arizona. (cnbc.com) Arizona matters because wafer plants without nearby packaging still leave a gap at the finish line. Taiwan Semiconductor Manufacturing Company said on March 4, 2025 that its United States investment would rise to $165 billion and include two advanced packaging facilities alongside new fabrication plants and a research center. (pr.tsmc.com) Intel is trying to sell an alternative route. Its foundry business offers advanced packaging tools including Embedded Multi-die Interconnect Bridge, which links chip pieces across a package, and Foveros, which stacks chips vertically to save space and shorten connections. (intel.com) But even if another company can package more chips, the squeeze does not stop at the packaging line itself. CNBC reported that the shortage spills into package substrates, specialty materials, and test services, because every finished module still has to be mounted, checked, and qualified before a cloud company can slide it into a server rack. (cnbc.com) That is why this bottleneck looks different from the chip shortages people learned about in 2021 and 2022. Back then the problem was often wafer capacity; in 2026, a company can have working silicon and still be stuck waiting for the factory step that turns separate dies and memory stacks into a shippable product. (cnbc.com)
