TSMC moves packaging to US
- TSMC said it will open a chip-packaging plant in Arizona, shifting more of the back-end work to the U.S. - The company is expanding CoWoS advanced packaging and plans a 14-reticle-size CoWoS that can link multiple compute dies and HBM stacks. - The move targets a persistent advanced-packaging bottleneck while TSMC also showed new process tech that delays use of ASML's costly high‑NA machines ( )
TSMC plans to open a chip-packaging plant in Arizona by 2029, moving another critical step of advanced chip production closer to its U.S. fabs. (usnews.com) The company’s packaging chief, Doug Yu, told Reuters the Arizona site would handle “advanced packaging,” the stage where separate pieces of silicon and memory are joined into one high-performance processor package. Reuters reported the timeline on April 22 from TSMC’s North America Technology Symposium in Santa Clara, California. (usnews.com) That step has become a choke point for artificial-intelligence chips. Reuters said modern processors from companies such as Nvidia are often built from several chiplets and high-bandwidth-memory stacks, then assembled with advanced packaging rather than as one giant chip. (usnews.com) TSMC had already signaled the move in January, when it said it was applying for permits to start construction of its first advanced-packaging plant in an existing Arizona facility. In March 2025, the company said it would raise planned U.S. investment to $165 billion, adding three new fabs, two advanced-packaging facilities and an R&D center. (usnews.com; tsmc.com) At the same April 22 symposium, TSMC said it is expanding Chip-on-Wafer-on-Substrate, or CoWoS, its main advanced-packaging platform for AI chips. The company said a new 14-reticle-size CoWoS design can connect 12 or more high-bandwidth-memory stacks with TSMC’s System-on-Wafer-X technology. (businesswire.com) TSMC also used the event to show new front-end manufacturing technology. Reuters reported its A13 process is designed to make smaller, faster chips without relying on ASML’s next-generation high-numerical-aperture lithography tools, which analysts have estimated at roughly $400 million each. (usnews.com) TSMC said A13 delivers up to 15% higher speed at the same power, or 30% lower power at the same speed, plus more than 20% logic density gain versus N2. The company said volume production is scheduled for the second half of 2028, and it separately introduced N2U for high-performance computing products that want better performance with the N2 design flow. (businesswire.com) The packaging move does not eliminate Taiwan’s central role in TSMC’s network, but it does add U.S. capacity where customers are asking for more local manufacturing. By 2029, Arizona is set to do more than print leading-edge chips; it is set to assemble the multi-die AI packages that turn those chips into finished accelerators. (usnews.com; tsmc.com)
