TSMC CoPoS panels could double Nvidia B200 density, easing packaging slot crunch
- TSMC’s CoPoS panel-packaging pilot line is on track for June completion, with Nvidia viewed as an early target as AI chips outgrow today’s wafer-based limits. - Supply-chain reports say a 12-inch wafer can fit only seven, and sometimes four, large AI packages; square panels are meant to raise utilization. - TSMC is targeting volume CoPoS production in 2028 to 2029 as packaging, not silicon, becomes the AI bottleneck. (trendforce.com)
Chip packaging is the step that bolts logic chips and memory together, and TSMC is now pushing a panel-based version called CoPoS for bigger AI modules. (trendforce.com) (tsmc.com) Today’s packaging work mostly uses round 300-millimeter wafers. CoPoS, short for chip-on-panel-on-substrate, swaps that round base for a square panel so more large packages can fit before they hit the edge. (trendforce.com) (markets.financialcontent.com) That matters because AI accelerators keep getting physically larger once you include high-bandwidth memory stacks and the interposer that links everything together. TrendForce, citing Commercial Times, said a standard 12-inch wafer can now hold just seven such packages, and in some cases as few as four. (trendforce.com) TSMC’s CoPoS pilot line has already started taking tools, with full line completion expected by June 2026. Small-volume trial production is slated for the second half of 2026, according to supply-chain reporting cited by MemoryMarket and TrendForce. (trendforce.com) (memorymarket.com) The near-term goal is not a consumer gadget. The target is the kind of oversized package used by Nvidia and other AI-chip designers, where the packaging floorplan has become almost as limiting as the chip design itself. (trendforce.com) (techpowerup.com) TrendForce said Nvidia’s Rubin GPU package reaches 5.5 times reticle scale, a measure of how far a design stretches past the area a lithography tool can expose in one shot. Bigger packages mean more wasted space on a round wafer. (trendforce.com) Some industry reports put TSMC’s first CoPoS panel at about 310 by 310 millimeters, close enough to existing 12-inch tooling to limit disruption while still improving usable area. Those same reports describe longer-term plans for larger panels and eventual glass substrates. (markets.financialcontent.com) (inf.news) TSMC has not publicly laid out CoPoS production specs in the way supply-chain reports have, but it has been explicit that advanced packaging is expanding with AI demand. At its April 22, 2026 North America Technology Symposium, TSMC said it continues to expand CoWoS to integrate more silicon in a single package. (tsmc.com) The risk is that larger panels bring larger mechanical problems. TrendForce, again citing supply-chain sources, said warpage as substrates get bigger is one of the main hurdles before high-volume manufacturing. (trendforce.com) If the pilot stays on schedule, the industry expectation is volume production in 2028 or 2029. The immediate promise is simpler: fit more giant AI packages on each production run and loosen one of Nvidia’s tightest supply constraints. (trendforce.com) (memorymarket.com)
