TSMC details 14‑reticle CoWoS roadmap
- Taiwan Semiconductor Manufacturing Co. said at its April 22 North America Technology Symposium that it is already producing 5.5-reticle CoWoS packages for AI chips. - TSMC said 14-reticle CoWoS will enter production in 2028, packing about 10 large compute dies and 20 high-bandwidth memory stacks in one package. - The roadmap pushes CoWoS beyond today’s size limits as AI systems demand more memory beside compute. (tsmc.com)
Chip packaging is the layer that wires separate pieces of silicon into one working module, and TSMC says those modules are getting much bigger. At its North America Technology Symposium on April 22, the company said it is already producing 5.5-reticle CoWoS packages for artificial intelligence chips. (tsmc.com) (focustaiwan.tw) A reticle is the maximum area a chip pattern can be exposed in one lithography shot, so packaging larger than one reticle is a way to stitch more silicon together after manufacturing. CoWoS, short for Chip on Wafer on Substrate, uses a silicon interposer as a high-density bridge between compute dies and high-bandwidth memory stacks. (tsmc.com 1) (tsmc.com 2) TSMC said a 14-reticle CoWoS package is slated for production in 2028 and will be able to integrate about 10 large compute dies and 20 high-bandwidth memory, or HBM, stacks. The company said it will follow that with CoWoS packages larger than 14 reticles in 2029. (tsmc.com) (focustaiwan.tw) That shift tracks how AI accelerators are being designed now: not as one giant chip, but as several compute tiles surrounded by stacks of memory. Bigger packages let designers place more compute and more HBM in the same module without moving to a full wafer-scale system. (tsmc.com 1) (tsmc.com 2) TSMC tied the larger CoWoS roadmap to its broader 3DFabric plan for AI and high-performance computing. In the same update, it said larger-than-14-reticle CoWoS and its SoW-X, or System-on-Wafer, technology are both targeted for 2029. (tsmc.com) (focustaiwan.tw) The company also used the symposium to outline the process nodes meant to feed those packages. TSMC said N2U is planned for production in 2028, while its A13 process and A12 with backside power delivery are both targeted for 2029. (tsmc.com) (focustaiwan.tw) Packaging is also becoming a business line of its own, not just a support step for wafers. TrendForce, citing Commercial Times and TSMC, reported on April 28 that TSMC is currently producing 5.5-reticle CoWoS and plans 14-reticle CoWoS by 2028, as advanced packaging revenue keeps rising. (trendforce.com) TSMC’s message was that the bottleneck in AI hardware is no longer only the transistor node. It is also how much compute and memory the package can hold, and how soon those larger packages can be built at volume. (tsmc.com) (trendforce.com)
