TSMC shifts focus to system-level AI
- TSMC used its April 22 North America Technology Symposium to pitch AI chipmaking as a system problem, pairing new logic nodes with packaging advances. - The company debuted A13 for 2029, added N2U for 2028, and said CoWoS packaging will integrate more silicon and memory in one package. - The shift tracks AI demand moving beyond transistor shrinks toward packaging and integration constraints. (tsmc.com)
Taiwan Semiconductor Manufacturing Co. used its April 22 North America Technology Symposium in Santa Clara to frame AI chipmaking around “transistor scaling to system integration.” (tsmc.com) That message came with a roadmap update: TSMC introduced its A13 logic process for 2029 and N2U, a 2-nanometer platform variant, for 2028. (tsmc.com) TSMC said A13 is a direct shrink of A14 with 6% area savings, while N2U is aimed at artificial intelligence, high-performance computing, and mobile chips. (tsmc.com) For AI chips, the package is the container that links compute dies and high-bandwidth memory into one working module. TSMC’s symposium agenda put CoWoS, InFO, SoIC, and system integration alongside 3-nanometer and 2-nanometer process updates. (tsmc.com) In its symposium release, TSMC said its 3DFabric packaging and 3D stacking roadmap is being expanded to fit more silicon in a single package. The company tied that directly to AI demand for more computing power and more memory. (tsmc.com) That emphasis matches TSMC’s financial results. In the quarter ended March 31, 2026, revenue reached US$35.90 billion, up 40.6% from a year earlier, and the company guided the next quarter to US$39.0 billion to US$40.2 billion. (investor.tsmc.com 1) (investor.tsmc.com 2) TSMC’s investor materials also show how concentrated that business has become in advanced chips. In the first quarter of 2026, 7-nanometer-and-below technologies made up 73% of wafer revenue. (investor.tsmc.com) Industry coverage of the symposium described the same shift in blunter terms: process nodes still matter, but AI systems are now constrained by memory links, power delivery, reticle limits, and packaging scale. (semiengineering.com) TSMC’s public line is not that transistor advances are over. It is that the next gains come from combining new nodes, backside power delivery, and larger multi-die packages into one manufacturing plan. (tsmc.com 1) (tsmc.com 2) That leaves TSMC selling customers more than a smaller transistor. It is selling the full stack needed to turn AI demand into shippable hardware. (tsmc.com)
