MediaTek CEO: "Solo Chip Era is Over"
At the ISSCC 2026 conference, MediaTek's CEO declared that the "solo chip era is over," advocating for a new industry focus on system-level efficiency. The statement reflects a broader pivot from maximizing individual component specifications to optimizing the performance of the entire system. This includes integrated considerations for power, thermal management, interconnects, and software.
- The shift away from monolithic chips is driven by the physical and economic limits of semiconductor manufacturing, such as reaching the maximum reticle size for a single die and the declining yield rates for very large, complex chips. This has pushed the industry toward heterogeneous integration, where systems are built by combining multiple smaller, specialized chips, known as "chiplets." - Advanced packaging is the key enabling technology for this system-level approach, with companies like TSMC offering a suite of solutions called 3DFabric. This platform includes technologies like CoWoS (Chip-on-Wafer-on-Substrate), which stacks high-bandwidth memory (HBM) with logic for AI accelerators, and SoIC (System-on-Integrated-Chips) for 3D stacking of chiplets with high-density vertical interconnects. - To ensure interoperability between chiplets from different vendors, an industry consortium including Intel, AMD, ARM, Google, Microsoft, Samsung, and TSMC has established the Universal Chiplet Interconnect Express (UCIe) standard. The UCIe 3.0 specification, released in August 2025, supports data rates up to 64 GT/s to meet the high-bandwidth demands of AI systems. - This "chiplet" strategy allows for a mix-and-match approach where different functions can be built on their most suitable and cost-effective process nodes—for example, integrating high-performance 5nm logic chiplets with analog I/O chiplets manufactured on a more mature 28nm process within the same package. - The explosive growth of AI is a primary catalyst for this trend, as AI accelerators demand massive memory bandwidth and computational power that is difficult to deliver with a single chip. Advanced packaging allows for tighter integration of logic and high-bandwidth memory, which is critical for training large AI models. - The title of MediaTek CEO Rick Tsai's plenary talk at ISSCC 2026 was “Advancing Horizons for AI: Perspectives on Semiconductor Innovations.” His presentation detailed how progress in AI systems depends on the co-optimization of advanced packaging, power delivery, thermal management, and high-bandwidth interconnects. - The growing importance of this system-level integration is reflected in market forecasts; the semiconductor packaging market is projected to grow from USD 54.99 billion in 2026 to USD 132.24 billion by 2035. - This system-level design philosophy requires a "shift-left" approach in the development process, where decisions about packaging, thermal performance, and power integrity are made early in the architectural phase, rather than after the chip is designed.
