Agentic AI tools for chip design

Chip design software is getting AI agents that can run pieces of the engineering workflow, not just answer questions. Cadence and NVIDIA said on March 17 they are rolling out joint tools for integrated-circuit and system design. (cadence.com) A chip design flow is a long chain of steps: engineers write logic, check that it works, place circuit blocks on silicon, route the wiring, and verify power, timing and manufacturability before tapeout. Cadence said the new offering targets both integrated-circuit design and “physical AI” systems, using NVIDIA accelerated computing underneath. (cadence.com) Cadence framed the shift as “Design for AI and AI for Design,” meaning it is both building chips for artificial-intelligence workloads and using artificial intelligence to automate chip work itself. NVIDIA said in a separate March 16 announcement that Cadence is among the industrial software companies building NVIDIA-powered agents to plan, optimize and verify chip and system workflows. (cadence.com) (nvidianews.nvidia.com) The basic pitch is speed. Cadence said the joint stack combines its design software with NVIDIA CUDA-X libraries, Omniverse technologies and GPU systems so engineers can run more compute-heavy optimization and simulation jobs in less time. (cadence.com) (nvidia.com) This arrives as electronic design automation vendors are trying to move beyond “copilot” features that suggest fixes and toward agents that can execute multi-step tasks. Cadence launched Cerebrus AI Studio in May 2025 as what it called an agentic, multi-block system-on-chip design platform, then introduced ChipStack AI Super Agent in February 2026 for design and verification workflows. (cadence.com 1) (cadence.com 2) Physical design is one of the places vendors think that automation can pay off fastest. That stage turns a logical circuit into a floorplan and wiring layout on silicon, and small changes can ripple into power use, clock speed and yield, which is why companies run repeated optimization loops before manufacturing. (cadence.com) Cadence widened the partnership again on April 15 at CadenceLIVE Silicon Valley, saying the two companies would deliver accelerated tools across agentic AI, physics-based simulation and digital twins for semiconductor design, physical AI systems and hyperscale AI factories. That put the March chip-design announcement inside a broader push to tie design software more tightly to NVIDIA computing infrastructure. (cadence.com) NVIDIA is making the same case with other software vendors, not just Cadence. Its March 16 release named Dassault Systèmes, PTC, Siemens and Synopsys alongside Cadence, and listed customers including MediaTek, Samsung, SK hynix and TSMC using NVIDIA-accelerated industrial software and tools. (nvidianews.nvidia.com) For chip teams, the near-term question is less whether an agent can “design a chip” end to end than which steps can be safely handed off. Cadence’s recent product releases focus on bounded jobs such as writing testbenches, creating test plans, orchestrating regression runs, debugging failures and optimizing multi-block system-on-chip work. (cadence.com 1) (cadence.com 2) The result is a tighter link between the companies that sell chip-design software and the company selling much of the hardware used to run modern AI. Cadence and NVIDIA are betting that the next gain in semiconductor productivity comes from agents that can keep iterating after the engineer gives the goal. (cadence.com 1) (cadence.com 2)