AMD pushes packaging alternatives

AMD’s May 21 announcement of more than $10 billion of Taiwan ecosystem investment put an obscure semiconductor step — advanced packaging — at the center of its AI buildout. The company said the spending will expand strategic partnerships and scale packaging manufacturing needed for next-generation AI infrastructure. (amd.com) AMD tied the effort directly to its “Venice” EPYC processors, MI450X accelerators and Helios rack-scale systems planned for deployment in the second half of 2026. ### Why is AMD talking about packaging instead of just chips? AMD said on May 21 that the investment is aimed at “silicon, packaging and manufacturing technologies” needed to deploy AI systems faster and at greater scale. (amd.com) The company said advanced packaging is now part of the production path for its next-generation infrastructure, not a back-end detail. Taipei Times reported on May 23 that Lisa Su told reporters in Taipei AMD was investing to ensure advanced packaging capacity over the next three years as AI infrastructure demand rises. Su said CoWoS is “a great technology,” but AMD is also looking for technologies that can optimize the cost of advanced packaging. (amd.com) ### What alternative is AMD building in Taiwan? AMD said it is working with ASE and SPIL to develop and qualify wafer-based 2.5D bridge interconnect technology built around elevated fan-out bridge, or EFB. The company also said it had qualified, with Powertech Technology Inc., what it described as the industry’s first 2.5D panel-based EFB interconnect. AMD said the architecture increases interconnect bandwidth and improves power efficiency. (amd.com) Lisa Su said in Taipei that EFB remains early in development and that AMD is investing in EFB capacity while also securing CoWoS capacity. Taipei Times said that positioning suggested EFB could serve as an alternative route to the CoWoS packaging technology developed by TSMC. (taipeitimes.com) ### Who are the Taiwan partners in this supply chain? AMD named ASE, SPIL and PTI on the packaging side, and said it is also working with system and manufacturing partners in Taiwan and globally. CNBC reported that AMD identified Sanmina, Wiwynn, Wistron and Inventec as companies helping build Helios. Bloomberg reported that AMD is also working with Powertech and Inventec to expand regional capabilities. (amd.com) Taipei Times listed additional Taiwan substrate suppliers in the local ecosystem, including Unimicron, Nan Ya Printed Circuit Board and Kinsus. That report said AMD’s packaging network in Taiwan now spans outsourced semiconductor assembly and test providers as well as substrate makers. (taipeitimes.com) ### Why does CoWoS matter so much here? Taipei Times reported that TSMC has spent the past two years expanding CoWoS capacity but has still faced bottlenecks because of strong AI-chip demand. The paper said Nvidia is the largest consumer of CoWoS capacity. AMD’s push into EFB comes as chip companies compete for packaging slots as well as wafer supply. (amd.com) AMD’s own statements stop short of saying it is replacing CoWoS. In Taipei, Su said AMD was “happy” with TSMC’s CoWoS progress and would continue allocating between EFB and CoWoS depending on demand. ### How does this connect to AMD’s product roadmap? AMD said “Venice,” its 6th-generation EPYC processor, has begun ramping production in Taiwan on TSMC’s 2-nanometer process, with future plans to ramp production at TSMC’s Arizona facility. (taipeitimes.com) The company said EFB-based 2.5D packaging is intended to support “Venice” CPUs and improve bandwidth and efficiency in AI systems. Helios is the near-term milestone. (taipeitimes.com) AMD said Helios racks combining “Venice” CPUs and MI450X GPUs are on track for multi-gigawatt deployments beginning in the second half of 2026, with packaging partners in Taiwan forming part of that ramp. (amd.com)