TSMC's packaging pivot

TSMC said it plans to add advanced chip packaging in Arizona by 2029, keeping a critical step in artificial intelligence chip production closer to its U.S. fabs. (usnews.com) The company disclosed the timeline on April 22 in Santa Clara, where deputy co-chief operations officer Kevin Zhang said construction had begun and the site would add CoWoS and 3D-IC packaging before 2029. Reuters reported many chips made in Arizona still go back to Taiwan for that final assembly step. (usnews.com) Packaging is the stage where several pieces of silicon are stacked or linked into one product, which is how Nvidia and other companies build many modern artificial intelligence processors. TSMC said at its 2026 Technology Symposium that its packaging roadmap includes CoWoS, InFO, SoIC and System-on-Wafer technologies. (tsmc.com) TSMC paired that Arizona move with a new manufacturing roadmap that stretches to 2029. At the same April 22 symposium, it introduced A13, a new logic process scheduled for production in 2029, with 6% area savings from A14 and full backward compatibility with A14 design rules. (tsmc.com) TSMC also previewed A12 for 2029 and N2U for 2028. The company said N2U offers 3% to 4% higher speed or 8% to 10% lower power than N2P, while A12 adds backside power delivery for artificial intelligence and high-performance computing chips. (tsmc.com) The manufacturing story and the packaging story are tied together because leading artificial intelligence chips now depend on both. Reuters reported packaging has become a supply bottleneck, even as TSMC’s Arizona fab already makes chips for customers including Apple and Nvidia. (usnews.com) TSMC’s roadmap also showed what it is not buying yet. Reports from the symposium said TSMC does not expect its A13 and A12 nodes to require ASML’s high-numerical-aperture extreme ultraviolet machines, which ASML says are its newest 0.55 NA EUV systems for tighter patterning. (trendforce.com (asml.com) That choice leaves TSMC leaning on design changes, packaging and existing lithography tools to keep improving chip performance. TSMC’s current A16 node, listed separately on its site, is aimed at high-performance chips and promises 8% to 10% higher speed or 15% to 20% lower power than N2P. (tsmc.com) Arizona will not be the only packaging option in the state. Reuters reported Amkor said last year it was working with Apple and Nvidia on an Arizona packaging plant targeted for mid-2027 construction completion and early 2028 production, while Zhang said TSMC was still discussing what technologies Amkor could offer customers. (usnews.com) For now, TSMC’s U.S. expansion still has a gap between making wafers and finishing them. The company’s answer is to close that gap by 2029, while pushing its next chip nodes forward without relying on ASML’s most expensive new tool. (usnews.com) (tsmc.com)