TSMC’s CoWoS roadmap expands to span 14+ reticles, boosting advanced‑packaging density
- Taiwan Semiconductor Manufacturing Co. used its April 22 North America Technology Symposium to map a bigger CoWoS packaging roadmap for AI chips through 2029. - TSMC said 14-reticle CoWoS enters production in 2028 with about 10 compute dies and 20 HBM stacks, then grows beyond 14 reticles. - The plan shifts AI scaling toward packaging and stacking, while TSMC also postpones High-NA EUV adoption through 2029. (tsmc.com) (bloomberg.com)
Modern AI chips are hitting a new limit: not just how small transistors get, but how much compute and memory can fit inside one package. TSMC says its next CoWoS designs will get much larger by 2028 and 2029. (tsmc.com 1) (tsmc.com 2) CoWoS stands for Chip on Wafer on Substrate, a way to place logic dies and high-bandwidth memory side by side on a shared base so they can exchange data faster than separate chips on a board. TSMC says the platform is built for high-performance computing and already supports larger-than-2X-reticle interposers in production offerings. (tsmc.com) At TSMC’s North America Technology Symposium in Santa Clara on April 22, the company said a 14-reticle CoWoS package is slated for production in 2028. TSMC said that version can integrate about 10 large compute dies and 20 HBM stacks. (tsmc.com) TSMC then said CoWoS will expand beyond 14 reticles in 2029. Reporting from the symposium said that next step is aimed at packages with as many as 24 HBM5E stacks and much higher aggregate bandwidth. (tomshardware.com) (computerbase.de) The company tied that packaging push directly to AI demand for more compute power and more memory in a single package. TSMC also said its 2029 roadmap includes SoIC 3D stacking options and a 40-reticle System-on-Wafer-X platform for even larger assemblies. (tsmc.com) (taipeitimes.com) That is a change from the old chip-industry script, where each leap was mostly framed around a new process node. TSMC’s April 2026 roadmap paired A13, A12 and N2U logic updates with packaging, stacking and integration as co-equal ways to raise system performance. (tsmc.com) (eetimes.com) TSMC reinforced that message by saying it has no current plan to use ASML’s High-NA extreme ultraviolet tools for production through 2029. Bloomberg reported Kevin Zhang said the machines, priced above €350 million each, are too expensive for TSMC’s planned nodes right now. (bloomberg.com) TSMC’s own roadmap shows how quickly the package sizes are growing. In April 2025, the company said 9.5-reticle CoWoS would reach volume production in 2027 with 12 or more HBM stacks; one year later, it mapped 14-reticle production for 2028 and a larger follow-on for 2029. (tsmc.com 1) (tsmc.com 2) The backdrop is a supply chain already strained by AI demand. TSMC’s packaging capacity has become a bottleneck for advanced GPUs and accelerators, and larger CoWoS designs would push more of the industry’s highest-end compute into a smaller set of customers that can secure both wafers and HBM. (trendforce.com) (digitimes.com) The packaging race is also colliding with security and equipment risk. DigiTimes reported on April 27 that a Taiwanese court sentenced a former TSMC engineer to 10 years in prison and fined Tokyo Electron Taiwan NT$150 million in a trade-secret case tied to semiconductor equipment know-how. (digitimes.com) TSMC’s roadmap now suggests the next AI chip battle will be decided as much by how many dies and memory stacks fit in one package as by transistor shrink alone. By 2029, the company is betting that bigger packages, denser stacks and cheaper scaling will matter more than buying the newest lithography tool first. (tsmc.com) (bloomberg.com)
