Rapidus Secures ¥267.6B for 2nm Chip Production
Japanese semiconductor consortium Rapidus announced it has secured ¥267.6 billion (approx. $1.8 billion) in a new funding round backed by the Japanese government and private companies. The capital is intended to help the company move from its current R&D phase toward mass production of 2-nanometer logic semiconductors by 2027.
This latest funding is part of a larger Japanese national strategy to reclaim a leading position in advanced semiconductors, backed by a consortium of eight major companies including Toyota, Sony, and SoftBank. The government's total commitment to the Rapidus project is expected to reach ¥3 trillion (approx. $19.3 billion), signifying a major public-private push to compete with industry giants like TSMC and Samsung. The government will hold "golden shares" in Rapidus, giving it veto power over major corporate decisions to ensure alignment with national economic security goals. Rapidus's core technology for the 2nm process is licensed from IBM, with over 150 Japanese engineers dispatched to IBM's Albany, New York research facility to learn the manufacturing steps. The company is also a core partner of Belgium's Imec, a leading R&D hub for nanoelectronics, giving it access to cutting-edge research and a global ecosystem of industry players. This strategy aims to leapfrog existing Japanese capabilities, which have fallen behind in leading-edge logic chip production. The company's go-to-market strategy hinges on more than just the advanced 2nm node; it's centered on a "Rapid and Unified Manufacturing Service" (RUMS). This model integrates front-end wafer fabrication and back-end packaging processes at its Chitose, Hokkaido facility to shorten turnaround times, a key pain point for fabless AI companies needing to iterate quickly. A key differentiator for Rapidus is its focus on "Design-Manufacturing Co-Optimization" (DMCO), a concept that tightly couples the chip design and manufacturing processes. By using a single-wafer processing approach, Rapidus can collect vast amounts of data to feed back into the design phase, leveraging AI and machine learning to improve yields and accelerate design cycles for its customers. The Hokkaido plant, dubbed IIM-1 (Innovative Integration for Manufacturing), is scheduled to begin pilot production in April 2025. Initial mass production capacity is slated to begin at 6,000 wafers per month in the latter half of 2027, with plans to scale to approximately 25,000 wafers per month within the first year of operation. Rapidus has already secured its first publicly announced customer for its 2nm process: Tenstorrent, the AI chip startup led by veteran CPU architect Jim Keller. The collaboration will focus on developing and manufacturing edge-AI accelerators, signaling Rapidus's focus on the high-growth AI hardware market. Tenstorrent, which also works with Samsung and TSMC, was attracted to Rapidus's focus on fast iteration speeds for taping out new designs. To enable its high-turnaround model, Rapidus is partnering with key EDA (Electronic Design Automation) vendors like Synopsys and Siemens. These collaborations will develop advanced, AI-driven design flows and process design kits (PDKs) specifically for the 2nm gate-all-around (GAA) process, aiming to reduce design iterations and accelerate time-to-market for fabless customers. Looking beyond 2nm, Rapidus has already signaled its ambition to stay on the cutting edge. The company plans to begin research and development on 1.4-nanometer technology next year, with construction for a second fab potentially starting in 2027. This aggressive roadmap underscores Japan's determination to not only re-enter the market but to become a long-term leader in advanced semiconductor manufacturing.
