Siemens deploys AI agents for chip design
Siemens has announced the integration of agentic AI into its Questa One platform to accelerate integrated circuit design and verification. The company says the AI-driven workflows can be configured with human expertise to speed up the register-transfer level (RTL) sign-off process. The goal is to help chip designers achieve faster results while preserving current investments.
The move is part of Siemens' broader strategy to embed generative and agentic AI across its entire Electronic Design Automation (EDA) platform. Mike Ellow, CEO of Siemens EDA, stated the company is strategically investing in sophisticated, industrial-grade AI solutions built specifically for the complexities of EDA. This AI integration aims to tackle the "Verification Productivity Gap," where the complexity of new chip designs outpaces the availability of skilled engineers and the capabilities of traditional tools. Industry data shows the rate of first-silicon success has dropped significantly, while the percentage of projects running behind schedule has increased, highlighting the need for a new approach. The AI agents within the Questa One platform perform tasks like generating structured test plans, predicting which simulation tests are most likely to fail, and automating debug analysis. For example, the "Stimulus-Free Verification" feature uses over 20 integrated engines and generative AI to reduce analysis time on complex system-on-a-chip (SoC) designs from over 24 hours to under a minute. Early adopters like MediaTek have reported significant productivity gains. Chienlin Huang, a senior technical manager at MediaTek, noted that the platform's generative AI saved weeks of engineering time and that its predictive capabilities saved days of regression and debugging time. Siemens' initiative is part of a wider industry trend of integrating AI into chip design. Competitors like Synopsys, with its DSO.ai, and Cadence with its Cerebrus AI, are also leveraging artificial intelligence to automate and optimize the complex process of semiconductor design and verification.
