TSMC roadmap update

TSMC said on April 22 it can keep shrinking chips through 2029 without using ASML’s newest high-NA lithography machines. (reuters.com) At its North America Technology Symposium in Santa Clara, TSMC introduced A13 for 2029 production, previewed A12 for 2029, and added N2U for 2028. A13 is a shrink of A14, while N2U is an added version of TSMC’s 2-nanometer family. (tsmc.com) TSMC said A13 cuts chip area by 6% versus A14 and keeps design rules backward-compatible with A14, which lets customers move existing designs more quickly. TSMC said N2U offers 3% to 4% higher speed or 8% to 10% lower power than N2P, with a 2% to 3% logic-density gain. (tsmc.com) Chip manufacturing uses lithography machines to print circuit patterns onto silicon, and ASML’s high-NA extreme-ultraviolet tools are the newest and most expensive version of that gear. Reuters reported those machines cost about $400 million each, roughly twice older EUV systems. (reuters.com) TSMC said it plans to keep extracting gains from its existing EUV fleet instead of moving to high-NA through this roadmap. Kevin Zhang, TSMC’s deputy co-chief operating officer and senior vice president, told Reuters the company’s research and development team had leveraged current EUV tools while keeping an aggressive scaling plan. (reuters.com) The roadmap is aimed at customers building artificial-intelligence and high-performance computing chips, where power use, speed and packaging now matter as much as transistor size. Reuters reported TSMC said it expects by 2028 to package 10 large compute chips with 20 stacks of high-bandwidth memory, up from systems such as Nvidia’s Vera Rubin with two compute chips and eight memory stacks. (reuters.com) TSMC’s earlier A16 plan had already centered on backside power delivery, which routes power from the back of the chip to free space for signal wiring on the front. On its product page, TSMC says A16 will provide an 8% to 10% speed gain or 15% to 20% lower power than N2P, with up to 1.10 times chip density. (tsmc.com) That makes A12 notable because TSMC said it will bring the same Super Power Rail backside-power approach to a later node in 2029. The company said A12 is being positioned for artificial intelligence and high-performance computing applications. (tsmc.com) TSMC’s message to customers was that smaller transistors are still coming, but the company is pairing those gains with packaging and power-delivery changes instead of betting on the costliest new toolset first. (reuters.com)