RISC-V Adoption Grows in Mainstream Tech

The open-source nature of RISC-V is a significant advantage for aerospace and defense, where verifiable security is paramount. Unlike proprietary ISAs, RISC-V allows for full inspection of the register-transfer level (RTL) source code, enabling designers to verify that there is no malicious code and establish a higher level of trust, which is critical for sensitive and high-risk military applications. This transparency is crucial for applications like secure data communications and other operations where confidentiality and authenticity are essential. For safety-critical systems, such as those in avionics, RISC-V's architecture offers advantages in achieving DO-178C compliance. The modularity of the instruction set architecture (ISA) allows developers to implement only necessary features, reducing complexity and potential attack surfaces. This simplicity aids in building deterministic systems, a key requirement for certification. Furthermore, the open architecture simplifies the implementation of dissimilar redundancy, a requirement for the highest safety assurance levels (DAL-A), by allowing for different processor configurations or diverse vendor solutions while maintaining architectural consistency. In consumer electronics, Google's Pixel 6 and later models utilize a custom-designed, RISC-V-based processor for their Titan M2 security chip. This dedicated, separate microprocessor handles security-critical tasks, isolating them from the main CPU to protect against malicious actors and a compromised application. The Titan M2 is responsible for protecting user data keys, hardening the secure boot process, and supporting Android StrongBox for tamper-resistant key storage. Meta is leveraging RISC-V to optimize its AI workloads, developing a family of custom ASICs called Meta Training and Inference Accelerators (MTIA). Finding GPUs not always optimal for their specific recommendation models, Meta designed these chips with processor cores based on the RISC-V ISA, which are heavily customized to efficiently handle the required compute and control tasks. The company is already using these chips for inference and has plans to expand their use for AI training, aiming to reduce reliance on third-party hardware. Tenstorrent is productizing its high-performance RISC-V CPU cores, known as Ascalon, for licensing. These cores are designed to compete with ARM's Neoverse and Cortex-A78, offering a drop-in replacement for ARM interfaces. In their AI accelerator cards, like the Grayskull e150, Tenstorrent uses a grid of "Tensix cores," each containing five small RISC-V cores to manage tasks, demonstrating a heterogeneous computing approach. The SERV project's bit-serial design is what makes it the world's smallest RISC-V CPU, trading speed for a smaller area by processing operations one bit per clock cycle. This minimal footprint makes it suitable for applications where silicon real estate is at a premium, such as IoT devices and even novel uses like cranial implants. The reference System-on-a-Chip for SERV, called Servant, is a basic platform capable of running the Zephyr Real-Time Operating System (RTOS).