Advanced Packaging Now Drives Datacenter Design
Advanced chip packaging like CoWoS has become a central pillar of AI datacenter architecture, dictating thermal management, bandwidth, and TCO. This shift is fueling related moves, with firms like ASML now expanding into AI chip packaging and advanced lithography to power next-gen hardware.
The bottleneck in AI is no longer just the chip, but the package it sits in. TSMC is aggressively expanding its CoWoS capacity, aiming for 130,000 wafers per month by late 2026, a nearly fourfold increase from late 2024 levels, to meet explosive demand for AI accelerators. This expansion is critical as the total demand for CoWoS is projected to hit 1 million wafers in 2026. This capacity crunch has created a massive opening for competitors. Intel's EMIB and Foveros packaging are emerging as viable alternatives, attracting second-tier ASIC vendors and even customers who fabricate their logic at TSMC. Intel's key advantages are available US-based capacity and a cost structure potentially hundreds of dollars cheaper per chip than CoWoS, which could sway customers like Google-MediaTek and Meta for their 2027 accelerators. The custom silicon trend among hyperscalers is set to grow at a 44.6% compound annual growth rate through 2033, more than double the rate of the GPU-based market. Companies like Marvell and Broadcom are carving out significant niches as design partners for these custom ASIC projects. Broadcom, for instance, is co-developing a massive fleet of custom accelerators for OpenAI in a deal potentially worth over $100 billion through 2029. High-Bandwidth Memory (HBM) is another critical piece of the puzzle, with packaging technology enabling its tight integration with processors. SK hynix currently dominates the HBM market with a 62% share, while Samsung, after falling to third place, is expected to rebound and exceed a 30% share in 2026 as it enters NVIDIA's supply chain for next-generation products. Underpinning this ecosystem are the equipment makers. ASML is strategically expanding beyond its core EUV lithography business into tools specifically for advanced packaging. The company has already shipped its first XT:260 scanner designed for back-end processes, which boasts up to four times the throughput of existing packaging lithography systems. The industry is also standardizing to accelerate this modular approach. The Universal Chiplet Interconnect Express (UCIe) is an open specification that allows chiplets from different vendors to be interoperably connected within a package. The recently updated UCIe 3.0 specification doubles the data transfer speeds, a critical step for creating a multi-vendor chiplet ecosystem. Startups are a key indicator of future directions, with companies like Tenstorrent, led by Jim Keller, raising significant funding to develop new AI architectures. Tenstorrent's business model includes licensing its RISC-V and AI IP, enabling more companies to develop custom silicon solutions without starting from scratch. Looking ahead, the industry is moving towards even more advanced concepts like co-packaged optics (CPO) and hybrid architectures that combine silicon with optical compute units to overcome the physical limitations of traditional electronics. These technologies, expected to see adoption towards the end of the decade, represent the next frontier in sustaining AI performance scaling.
