TSMC pivots to co‑design and packaging
- Taiwan Semiconductor Manufacturing Co. used its April 22 North America Technology Symposium to extend its process roadmap to 2029, adding A13, A12 and N2U while putting packaging and co-design beside node shrinks. - TSMC said A13 is a direct shrink of A14 with 6% area savings, while N2U is slated for 2028 with 3%-4% speed gains or 8%-10% lower power than N2P. - The shift comes as TSMC posted $35.9 billion in first-quarter 2026 revenue and partners Cadence and Siemens pushed AI-assisted design and 3D packaging tools into the same roadmap. (tsmc.com)
A chip node is the recipe for building transistors, but the package is the box and wiring that lets many chips work as one computer. TSMC spent its April 22 symposium saying both now matter. (tsmc.com 1) (tsmc.com 2) Taiwan Semiconductor Manufacturing Co. extended its roadmap through 2029 at its North America Technology Symposium, adding A13, A12 and N2U to its lineup. The company framed the plan around “transistor scaling to system integration.” (tsmc.com 1) (tsmc.com 2) TSMC said A13 is a direct shrink of A14, the process it introduced in 2025. The company said A13 delivers 6% area savings and is aimed at artificial intelligence, high-performance computing and mobile chips. (tsmc.com 1) (tsmc.com 2) TSMC also added N2U, an extension of its 2-nanometer family scheduled for production in 2028. The company said N2U uses design-technology co-optimization to deliver 3% to 4% higher speed or 8% to 10% lower power, plus 1.02x to 1.03x logic density versus N2P. (tsmc.com) (businesswire.com) A12 is scheduled for 2029, and outside reports on TSMC’s presentation said A16 volume production moved to 2027 to match customer product timing. TSMC’s public release highlighted A13 and N2U but did not detail A12 specifications in the same way. (tsmc.com) (tech.yahoo.com) Packaging is the other half of the pitch. TSMC’s CoWoS technology links multiple dies on an interposer for artificial intelligence systems, and the company’s symposium materials put “system integration” alongside transistor scaling as a core theme. (tsmc.com) (tsmc.com) That message lines up with TSMC’s finances. The company reported first-quarter 2026 revenue of $35.90 billion on April 16, above guidance, and guided second-quarter revenue to $39.0 billion to $40.2 billion as artificial intelligence demand stayed strong. (tsmc.com) (tsmc.com) Electronic design automation companies are moving with TSMC. Cadence said on April 22 that it expanded its work with TSMC to provide IP, signoff-ready infrastructure and certified flows for N3, N2, A16 and A14, with a focus on reducing design iterations for AI and high-performance chips. (cadence.com) Siemens said the same day that it is working with TSMC on AI-powered automation across the design workflow, including automated design-rule-check fixing and system integration. Siemens also said its toolset won certifications for N3A, N3C, N2P, A16 and A14. (siemens.com) The practical change is that shrinking one chip is no longer the whole job. TSMC is selling a stack: a leading-edge logic node, software that helps customers fit designs to that node, and packaging that ties compute and memory together. (tsmc.com) (cadence.com) (siemens.com) TSMC’s roadmap now runs to 2029, but the immediate signal came this week in Santa Clara: the foundry wants customers to buy a system plan, not just a smaller transistor. (tsmc.com) (tsmc.com)
