TSMC Delays ASML High-NA
- TSMC demonstrated smaller, faster chips without adopting ASML's expensive high-NA EUV machines, citing cost concerns. - The company delayed high-NA EUV adoption through 2029 and updated its process roadmap while announcing packaging priorities. - TSMC also plans a chip-packaging plant in Arizona by 2029, signalling advanced packaging's central role for multi-die AI chips (reuters.com).
TSMC said on April 22 it will keep making its next wave of smaller chips without ASML’s newest high-NA machines, pushing any adoption beyond 2029. (reuters.com) At its North America Technology Symposium in Santa Clara, TSMC said its A14 process is still on track for production in 2028, with up to 15% higher speed at the same power or up to 30% lower power at the same speed than N2, plus more than 20% higher logic density. (tsmc.com) TSMC Deputy Co-Chief Operating Officer Kevin Zhang said the company’s A13 process will enter production in 2029, and Bloomberg reported TSMC has no current plan to use ASML’s high-numerical-aperture extreme ultraviolet tools through that year. (bloomberg.com) High-NA is a chipmaking lens upgrade: ASML says its first 0.55 numerical-aperture system can print features 1.7 times smaller in a single exposure than earlier EUV systems, which can cut some manufacturing steps. (asml.com) TSMC’s argument is that the math does not work yet. Reuters reported Zhang said high-NA would not create enough benefit to justify its cost, while Bloomberg said each machine sells for more than €350 million, or about $410 million. (reuters.com) (bloomberg.com) The company spent the same event pushing a different bottleneck: packaging, the step that links several chips and stacks of memory into one finished processor. TSMC said it will bring 9.5-reticle CoWoS packaging into volume production in 2027, enough to integrate 12 high-bandwidth-memory stacks or more with leading-edge logic. (tsmc.com) That matters for artificial-intelligence chips because many top processors are no longer one big die. Reuters reported Nvidia’s current flagship graphics processors use two large chips stitched together, and its Rubin Ultra chips due in 2027 will stitch four together. (reuters.com) TSMC also told Reuters it plans to open a chip-packaging plant in Arizona by 2029. The company’s Arizona site already includes plans for six wafer fabs, two advanced packaging facilities and an research-and-development center, according to TSMC. (reuters.com) (tsmc.com) The split in strategy is now clearer: Intel has been the earliest public backer of high-NA, while TSMC is trying to extend older EUV tools and put more money into advanced packaging. TSMC’s next test is whether customers still get the smaller, faster chips they want before 2029 without paying for ASML’s newest machine. (reuters.com) (asml.com)
