Renesas Unveils New Automotive Chips and Memory
Renesas is expanding its automotive offerings with new technologies for next-generation vehicle ECUs. The company unveiled a 3nm FinFET ternary content-addressable memory (TCAM) designed for high density and functional safety at ISSCC 2026. Renesas also presented three new SoC technologies aimed at multi-domain, software-defined vehicle architectures.
- The new 3nm TCAM achieves an industry-leading memory density of 5.27 Mb/mm² and is designed for scalability, allowing configurations as large as 256-bit × 4,096 entries by combining smaller, compiler-supported hard macros. - To reduce power consumption in the TCAM, Renesas implemented a two-stage pipelined search that uses an "all-mismatch detection" circuit; this approach can cut search energy by up to 71.1% by preventing the second stage from running if no potential match is found. - One of the new SoC technologies is a chiplet architecture that supports the highest level of automotive functional safety, ASIL D. It combines the standard UCIe die-to-die interface with a proprietary "RegionID" mechanism to prevent hardware interference between different applications running on the chiplets. - To handle the increasing size of AI accelerators (neural processing units) in automotive SoCs, which has grown 1.5 times compared to previous generations, Renesas redesigned the clock architecture. It uses distributed mini clock pulse generators (mCPGs) at the sub-module level to reduce clock latency and ensure timing requirements are met. - The announced SoC technologies include an advanced power gating system with over 90 distinct power domains, enabling precise control of power from milliwatts to tens of watts depending on the operating conditions. This design reduces IR drop by about 13% compared to conventional layouts. - These technologies are being integrated into Renesas's R-Car X5H SoC, which is designed to be a computational core for multi-domain ECUs that combine automated driving, digital cockpit, and connectivity functions on a single platform. - The chiplet architecture's UCIe interface was tested and shown to achieve a high transmission speed of 51.2 GB/s, which approaches the upper limits of transfer speeds typically seen within a single, non-chiplet-based SoC. - For the TCAM, Renesas enhanced functional safety to meet the ISO 26262 standard by adding dedicated SRAM for ECC parity with an independent address decoder, which improves the detection of incorrect address selection during write operations.
