VIS joins CoWoS interposer chain

Silicon interposers are the quiet piece underneath the AI boom. They are the thin slabs that let multiple chips sit side by side and talk at very high bandwidth inside advanced packages like CoWoS. The problem is that this layer has become a bottleneck, not just the GPUs themselves. Now Vanguard International Semiconductor, or VIS, says its Singapore fab will start making those interposers with TSMC technology support — a small-sounding manufacturing change that actually says a lot about where the AI supply chain is straining. (digitimes.com) ### What is VIS actually doing? VIS said on May 5 that it is adjusting the product mix at its new 12-inch Singapore fab to make silicon interposers used in advanced packaging for AI chips. The fab will license and transfer the related technology from TSMC, and some manufacturing equipment will be supplied by the customer. This is not VIS buil(digitimes.com)that stack. (digitimes.com) ### What is an interposer, in plain English? Think of an interposer as a super-dense wiring floor. Instead of cramming every function onto one giant chip, chip designers can place several dies — logic, I/O, memory interfaces — on top of this silicon base and connect them with very short, very fast links. That is the whole trick behind modern (digitimes.com)at makes the package work. (digitimes.com) ### Why does Singapore matter here? Because geography is part of the product now. The Singapore fab is operated by VSMC, the VIS-NXP joint venture announced in 2024, and it gives customers another place to source this infrastructure outside Taiwan. TrendForce notes that customer demand is tied not just to AI growth but also to diversification(digitimes.com)re than one place. (taipeitimes.com) ### What is the catch? Interposers eat into throughput. VIS cut the fab’s planned installed capacity to 44,000 12-inch wafers per month from 55,000 because the new product mix is more complex. So this is not a free expansion. The company is trading some broad mature-node output for a more strategic, higher-value role in advanced packaging infrastructure. (([taipeitimes.com)### When does this show up in real production? The Singapore fab is slated for volume production in the first quarter of 2027. More than 200 tools have already been moved in for trial production, and VIS says the first-phase 44,000-wafer capacity is already sold out under a long-term customer agreement. That is the strongest signal in the whole story — demand is concrete enough that the line is effectively spoken for before full ramp. (taipeitimes.com) ### Why is TSMC involved if VIS is making them? Because TSMC still sits at the center of the ecosystem. VIS is 27%-owned by TSMC, and the Singapore line depends on TSMC technology transfer. TSMC has been pushing hard to expand advanced packaging broadly, not just front-end wafer capacity, because packaging has become one of the limiting steps for AI systems. VIS gives TSMC a way to widen that pipe through an affiliated manufacturer. (taipeitimes.com) ### Does this mean the bottleneck is solved? No — but it does show the bottleneck has moved. A few years ago the hard part was mostly leading-edge compute wafers. Now the hard part is increasingly the industrial plumbing around them — interposers, advanced packaging lines, and the supply chain that feeds high-bandwidth chiplet designs. VIS joining that chai(taipeitimes.com)e infrastructure. (digitimes.com) ### Bottom line? This is really a story about AI hardware maturing. When a mature-node foundry in Singapore starts retooling for interposers with TSMC’s help, the message is clear: advanced packaging is no longer the last exotic step after the “real” chip is made. It is now one of the main factories the industry has to scale. (taipeitimes.com)