TSMC A13 and Packaging
- TSMC announced a new A13 process and clarified packaging plans that outline the next hardware envelope for chips. - The company says A13 is a shrink of A14 with roughly a 6% area reduction and targets production in 2029. - TSMC also plans a chip-packaging plant in Arizona by 2029 while AI-driven demand is keeping node capacity tight through 2027 ( ).
Taiwan Semiconductor Manufacturing Co. used its annual North America symposium on April 22 to sketch out two deadlines at once: a new A13 chipmaking process for 2029 and an Arizona advanced-packaging plant by 2029. (businesswire.com) (finance.yahoo.com) Chipmaking shrinks the circuits on a silicon wafer; packaging is the later step that connects finished pieces into one working processor. TSMC said modern artificial-intelligence chips increasingly depend on advanced packaging because many of them are built from several chiplets rather than one large die. (finance.yahoo.com) TSMC said A13 is a direct shrink of A14, the company’s 2025 node, and that it delivers 6% area savings over A14. The company also said A13 keeps A14’s design rules, which lets customers move existing designs over with less rework, and targets production in 2029. (businesswire.com) At the same event in Santa Clara, deputy co-chief operations officer Kevin Zhang told Reuters that TSMC has started construction tied to an Arizona packaging buildout. Zhang said the site will add CoWoS and 3D integrated-circuit capability before 2029. (finance.yahoo.com) CoWoS, short for chip-on-wafer-on-substrate, is one of the steps that lets companies place logic chips and high-bandwidth memory side by side on a shared base. That has turned packaging into a choke point for Nvidia-class artificial-intelligence systems, because the limiting factor is no longer only how many wafers TSMC can process. (finance.yahoo.com) The Arizona timing also shows how far the U.S. site is moving beyond front-end wafer production. Reuters reported that Apple and Nvidia already source chips from TSMC’s Arizona factory, but many of those chips still go back to Taiwan for packaging. (finance.yahoo.com) TSMC’s comments come one week after its April 16 first-quarter 2026 earnings call, where the company said first-quarter revenue reached $35.9 billion and that demand for advanced nodes remained strong enough for management to raise its full-year growth outlook. (investor.tsmc.com) The company used the symposium to show that the next bottleneck is not just the transistor, but the full hardware stack around it. By 2029, TSMC is planning to offer both a denser leading-edge node and a U.S. packaging route to assemble the kinds of multi-chip processors that artificial-intelligence customers are already ordering faster than suppliers can add capacity. (businesswire.com) (finance.yahoo.com)
