Logic density shifts

Optical computing is moving from lab demos toward a narrower job: speeding up the math-heavy front end of artificial intelligence inference while using far less power. (arxiv.org) In these systems, light carries numbers through waveguides and interferes to perform matrix multiplications, the repeated multiply-and-add work that dominates many neural-network layers. Researchers at the University of Texas at Austin and Arizona State University wrote in an April 2026 review that integrated photonics is being pitched as a way to relieve power, memory, and interconnect bottlenecks that electronic chips now hit first. (arxiv.org) That interest has shifted from general claims to workload-specific designs. A September 2025 paper from Massachusetts Institute of Technology researchers described a compiler for hybrid photonic-electronic large language model inference and reported simulated latency gains above 10 times and energy cuts up to 50% on prefill workloads under its hardware assumptions. (arxiv.org) Another October 2025 paper from researchers at the University of Texas at Austin proposed a co-design approach called ENLighten for Transformer models. The paper said its compressed model and reconfigurable photonic accelerator improved energy-delay product by 2.5 times over a prior photonic Transformer accelerator on a vision benchmark, with about a 1% accuracy drop after pruning 50% of a base Vision Transformer. (arxiv.org) The immediate target is inference, not training. The prefill step in a large language model reads the whole prompt at once and is compute-heavy, while later token-by-token decoding leans harder on memory bandwidth, a split that has pushed chip designers toward specialized hardware for each phase. (arxiv.org; arxiv.org) That is where optical hardware fits best today: dense linear algebra that can be run in parallel, with the rest of the model still handled by electronic logic. The same April 2026 review said end-to-end gains depend on cross-layer design, because electro-optic conversion, data movement, and limited on-chip photonic resources can erase raw device-level advantages. (arxiv.org; arxiv.org) At the same time, mainstream chipmakers are squeezing more performance out of packaging as transistor scaling gets harder. Semiconductor Engineering reported that 3.5D packaging, which stacks logic chiplets while bonding them onto a shared substrate, has emerged as a middle ground between 2.5D and full 3D integration because it can add SRAM, shorten signal paths, and ease some thermal problems. (semiengineering.com) Imec’s roadmap points the same way on the process side. In articles published in 2024 and 2026, imec said the nanosheet era is being extended from 2 nanometer-class nodes to the A10 node with outer-wall forksheet devices, before complementary field-effect transistors, or CFETs, take over at A7 and beyond; imec has separately described CFET as a beyond-1-nanometer option. (imec-int.com; imec-int.com; imec-int.com) A smaller camp is also revisiting reversible and adiabatic logic, which tries to avoid wasting energy as heat by switching more gradually and recovering charge instead of dumping it. Semiconductor Engineering reported in August 2025 that startup Vaire was still a couple of years from commercial availability, underscoring how early that path remains compared with packaging and accelerator work already in the market. (semiengineering.com) The result is not one replacement for silicon but a broader split in where performance comes from. More of the gains are now being sought in packaging, memory placement, and specialized compute blocks — including optical ones — rather than from transistor shrink alone. (semiengineering.com; arxiv.org)