Packaging is the choke point
The industry’s tightest bottleneck has shifted from wafer starts to advanced packaging, where combining memory and compute into dense modules is straining capacity. TSMC’s CoWoS packaging capacity is reportedly expanding at an 80% CAGR as customers demand tighter integration, and upstream substrate materials like ABF are showing strain as larger AI chips increase substrate area needs. (alltoc.com) (x.com)
A modern artificial intelligence chip is no longer one slab of silicon. Nvidia’s systems now split the job between a graphics processor and stacks of high-bandwidth memory, then wire them together inside one package with thousands of tiny connections. (cnbc.com) That package is the part now jamming up the line. CNBC reported on April 8, 2026 that Nvidia has reserved most of Taiwan Semiconductor Manufacturing Company’s most advanced packaging capacity, turning the final assembly step into the new limit on how many AI chips can ship. (cnbc.com) The key process is called Chip on Wafer on Substrate, which means a chip is mounted on a silicon base and then attached to a larger carrier board. Taiwan Semiconductor Manufacturing Company says this method is built for high-performance computing and lets one package combine leading logic chips with multiple memory stacks. (tsmc.com) Think of the substrate as the motherboard under the chip package. Ajinomoto says its Ajinomoto Build-up Film is the insulating layer used in the complex substrates under many high-performance processors, including the kind used in servers and personal computers. (ajinomoto.com) The squeeze gets worse as each new AI processor grows wider. At its April 23, 2025 Technology Symposium, Taiwan Semiconductor Manufacturing Company said it plans to bring 9.5-reticle-size Chip on Wafer on Substrate into volume production in 2027, large enough for 12 high-bandwidth memory stacks or more in one package. (tsmc.com) Bigger packages do not just consume more factory time. They also consume more substrate area, more insulating film, and more precision drilling and layering in the board underneath, so a bottleneck at packaging spreads backward into materials and substrate suppliers. (ajinomoto.com) (cnbc.com) That is why suppliers one step upstream are suddenly in focus. Digitimes reported in February 2026 that Unimicron said high-end Ajinomoto Build-up Film substrates for artificial intelligence applications were in strong demand, with fiberglass shortages still affecting the market. (digitimes.com) Kinsus, another substrate maker, told investors that artificial-intelligence-related applications had grown significantly even during the broader downturn in Ajinomoto Build-up Film substrate demand. By March 2026, coverage of its earnings call said Ajinomoto Build-up Film utilization could rise to 90% to 95% by the end of 2026. (kinsus.com.tw) (finance.biggo.com) Taiwan Semiconductor Manufacturing Company is trying to outrun the choke point with speed as well as spending. TrendForce reported in January 2025 that TSMC Vice President Jun He said Chip on Wafer on Substrate capacity was on track for more than 50% compound annual growth from 2022 to 2026, while factory build times had been cut from three to five years down to about one and a half to two years. (trendforce.com) The result is a chip industry where the hardest part is no longer etching smaller transistors. It is fitting giant compute dies, giant memory stacks, and giant substrates into one working module fast enough to keep up with demand from Nvidia, cloud companies, and everyone else chasing AI capacity. (cnbc.com) (tsmc.com)
